P87LPC767BN NXP Semiconductors, P87LPC767BN Datasheet - Page 23

• Manufacturer Part Number: P87LPC767BN
• Description: MCU 8-Bit 87LP 80C51 CISC 4KB EPROM 3.3V/5V 20-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

Specifications of P87LPC767BN

• Package: 20PDIP
• Device Core: 80C51
• Family Name: 87LP
• Maximum Speed: 20 MHz
• Ram Size: 128 Byte
• Program Memory Size: 4 KB
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 18
• Interface Type: I2C/UART
• On-chip Adc: 4-chx8-bit
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 2

Philips Semiconductors
External Interrupt Inputs
The P87LPC767 has two individual interrupt inputs as well as the
Keyboard Interrupt function. The latter is described separately
elsewhere in this section. The two interrupt inputs are identical to
those present on the standard 80C51 microcontroller.
The external sources can be programmed to be level-activated or
transition-activated by setting or clearing bit IT1 or IT0 in Register
TCON. If ITn = 0, external interrupt n is triggered by a detected low
at the INTn pin. If ITn = 1, external interrupt n is edge triggered. In
this mode if successive samples of the INTn pin show a high in one
cycle and a low in the next cycle, interrupt request flag IEn in TCON
is set, causing an interrupt request.
Since the external interrupt pins are sampled once each machine
cycle, an input high or low should hold for at least 6 CPU Clocks to
ensure proper sampling. If the external interrupt is
2002 Mar 25
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
EWD
WDT
EBO
CM2
ADC
CM1
BOF
EKB
EAD
EX0
EX1
KBF
EC2
EC1
IE0
IE1
Figure 11. Interrupt Sources, Interrupt Enables, and Power Down Wakeup Sources
RI + TI
ATN
TF0
ET0
TF1
ET1
EI2
ES
20
transition-activated, the external source has to hold the request pin
high for at least one machine cycle, and then hold it low for at least
one machine cycle. This is to ensure that the transition is seen and
that interrupt request flag IEn is set. IEn is automatically cleared by
the CPU when the service routine is called.
If the external interrupt is level-activated, the external source must
hold the request active until the requested interrupt is actually
generated. If the external interrupt is still asserted when the interrupt
service routine is completed another interrupt will be generated. It is
not necessary to clear the interrupt flag IEn when the interrupt is
level sensitive, it simply tracks the input pin level.
If an external interrupt is enabled when the P87LPC767 is put into
Power Down or Idle mode, the interrupt will cause the processor to
wake up and resume operation. Refer to the section on Power
Reduction Modes for details.
(FROM IEN0
REGISTER)
EA
P87LPC767
INTERRUPT
(IF IN POWER
TO CPU
WAKEUP
SU01401
DOWN)
Product data