EX256-TQG100 Actel, EX256-TQG100 Datasheet - Page 8

• Manufacturer Part Number: EX256-TQG100
• Manufacturer: Actel

Clock Resources
eX’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from
the HCLK buffer to the clock select MUX in each R-cell.
HCLK cannot be connected to combinational logic. This
provides a dedicated propagation path for the clock signal
for the automotive-grade eX devices. The hardwired clock
is tuned to provide a clock skew of less than 0.1 ns worst
case. If not used, the HCLK pin must be tied Low or High
and must not be left floating.
clock circuit used for the constant load HCLK.
HCLK does not function until the fourth clock cycle each
time the device is powered up to prevent false output
levels due to any possible slow power-on-reset signal and
fast start-up clock circuit. To activate HCLK from the first
cycle, the TRST pin must be reserved in the Designer
software and the pin must be tied to GND on the board.
(See the
page
The remaining two clocks (CLKA, CLKB) are global routed
clock networks that can be sourced from external pins or
Figure 1-6 • eX Routed Clock Buffer
Table 1-1 • Connections of Routed Clock Networks, CLKA
1 -4
Module
C-Cell
R-Cell
I/O Cell
eX Automotive Family FPGAs
1-24).
"TRST, I/O Boundary Scan Reset Pin" section on
and CLKB
CLKA, CLKB, S0, S1, PSET, and CLR
A0, A1, B0 and B1
Figure 1-5
Pins
EN
describes the
CLKBUF
CLKBUFI
CLKINT
CLKINTI
v3.2
from internal logic signals (via the CLKINT routed clock
buffer) within the eX device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB is sourced from internal logic signals, the
external clock pin cannot be used for any other input
and must be tied Low or High and must not float.
Figure 1-6
devices.
Table 1-1
routed clock networks, CLKA and CLKB.
Unused clock pins must not be left floating and must be
tied to High or Low.
Figure 1-5 • eX HCLK Clock Pad
describes the CLKA and CLKB circuit used in eX
describes the possible connections of the
From Internal Logic
Clock Network
HCLKBUF
Constant Load
Clock Network