EX256-TQG100 Actel, EX256-TQG100 Datasheet - Page 23

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EX256-TQG100

Manufacturer Part Number
EX256-TQG100
Description
Manufacturer
Actel
Datasheets

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Input Buffer Delays
Table 1-14 • Input Buffer Delays
Cell Timing Characteristics
Figure 1-17 • Flip-Flops
In
Out
GND
PAD
t
PRESET
1.5 V
INY
CLR
CLK
Q
3V
D
50%
INBUF
1.5 V
V CC
t
INY
t
SUD
0V
Y
50%
t
t
CLK
HPWH
RPWH
(Positive edge triggered)
D
,
t
HD
v3.2
PRESET
t
CLR
RCO
C-Cell Delays
Table 1-15 • C-Cell Delays
Q
S, A, or B
Out
GND
Out
t
HPWL
t
CLR
t
WASYN
,
t
50%
RPWL
t
t
H P
PD
t
50%
PD
50%
50%
V
V
CC
CC
eX Automotive Family FPGAs
S
A
B
GND
t
t
PRESET
PD
t
PD
GND
50%
Y
50%
V
CC
1-19

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