SI3201-GSR Silicon Laboratories Inc, SI3201-GSR Datasheet - Page 41
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SI3201-GSR
Manufacturer Part Number
SI3201-GSR
Description
SLIC 3.3V/3.3V/3.3V/5V/5V/5V
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3201-GSR.pdf
(122 pages)
Specifications of SI3201-GSR
Lead Free Status / Rohs Status
Compliant
- Current page: 41 of 122
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To configure the ProSLIC for trapezoidal ringing, the
user should follow the same basic procedure as in the
Sinusoidal Ringing section, but using the following
equations:
RCO is a value which is added or subtracted from the
waveform to ramp the signal up or down in a linear
fashion. This value is a function of rise time, period, and
amplitude, where rise time and period are related
through the following equation for the crest factor of a
trapezoidal waveform.
where T = ringing period, and CF = desired crest factor.
For example, to generate a 71 V
signal, the equations are as follows:
For a crest factor of 1.3 and a period of 0.05 s (20 Hz),
the rise time requirement is 0.0153 s.
RNGY 20 Hz
Figure 22. Trapezoidal Ringing Waveform
RNGX 71 V
V
TIP-RING
V
RCO 20 Hz, 1.3 crest factor
ROFF
=
RNGX
RNGY
------------------------------------- -
0.0153 8000
2
PK
t
RCO
=
RISE
24235
1
-- -
2
=
=
=
t
Desired V
-----------------------------------
RISE
--------------- -
20 Hz
=
=
71
----- -
96
1
-- -
2
1
3
-- - T 1
4
-------------------------------- -
t
RISE
96 V
2 RNGX
Period
=
2
T=1/freq
15
396
–
8000
=
---------- -
CF
8000
PK
=
24235
1
2
018Ch
8000
=
PK
2
200
15
, 20 Hz ringing
=
5EABh
=
time
C8h
Rev. 1.0
In addition, the user must select the trapezoidal ringing
waveform by writing TSWS = 1 in direct Register 34.
2.4.4. Ringing DC Voltage Offset
A dc offset can be added to the ac ringing waveform by
defining the offset voltage in ROFF (indirect Register 6).
The offset, V
RVO is set to 1 (direct Register 34, bit 1). The value of
ROFF is calculated as follows:
2.4.5. Linefeed Considerations During Ringing
Care must be taken to keep the generated ringing signal
within the ringing voltage rails (GNDA and V
maintains proper biasing of the external bipolar
transistors. If the ringing signal nears the rails, a
distorted ringing signal and excessive power dissipation
in the external transistors will result.
To prevent this invalid operation, set the V
(direct Register 74) to a value higher than the maximum
peak ringing voltage. The discussion below outlines the
considerations and equations that govern the selection
of the V
voltage.
First, the required amount of ringing overhead voltage,
V
current through the load, I
gain of Q5 and Q6, and a reasonable voltage required
to keep Q5 and Q6 out of saturation. For ringing signals
up to V
However, to determine V
equations below.
where:
N
I
(max value = 2 mA), and
V
It is good practice to provide a buffer of a few more
milliamperes for I
leakages, etc. The total I
smaller than 80 mA.
where
transistors Q5 and Q6.
The minimum value for V
following equation:
OS
AC,PK
OVR
REN
I
is the offset current flowing in the line driver circuit
LOAD,PK
, is calculated based on the maximum value of
is the ringing REN load (max value = 5),
= amplitude of the ac ringing waveform.
BATH
V
OVR
PK
is the minimum expected current gain of
=
= 87 V, V
setting for a particular desired peak ringing
ROFF
=
V
------------------ -
R
I
AC,PK
LOAD
LOAD,PK
ROFF
, is added to the ringing signal when
LOAD,PK
+
OVR
I
OS
=
OVR
BATH
LOAD,PK
------------ -
V
----------------- -
to account for possible line
= 7.5 V is a safe value.
=
LOAD,PK
ROFF
+
96
for a specific case, use the
1
V
is, therefore, given by the
AC,PK
80.6
, the minimum current
2
15
current should be
----------------- -
6.9 k
+
N
Si3216
1 V
REN
BATH
+
I
BAT
OS
value
) to
41
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