AT32UC3C2512C-Z2ZR Atmel, AT32UC3C2512C-Z2ZR Datasheet - Page 39
AT32UC3C2512C-Z2ZR
Manufacturer Part Number
AT32UC3C2512C-Z2ZR
Description
Microcontrollers (MCU) 512KB FL,-40/125oC AUTO
Manufacturer
Atmel
Datasheet
1.AT32UC3C1512C-AZR.pdf
(106 pages)
Specifications of AT32UC3C2512C-Z2ZR
Lead Free Status / Rohs Status
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5. Memories
5.1
9166BS–AVR-02/11
Embedded Memories
•
•
•
Internal High-Speed Flash (See
Internal High-Speed SRAM, Single-cycle access at full speed (See
Supplementary Internal High-Speed System SRAM (HSB RAM), Single-cycle access at full speed
– 512 Kbytes
– 64 Kbytes
– Memory space available on System Bus for peripherals data.
– 4 Kbytes
• 0 Wait State Access at up to 25 MHz in Worst Case Conditions
• 1 Wait State Access at up to 50 MHz in Worst Case Conditions
• Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding
• Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation
• 10 000 Write Cycles, 15-year Data Retention Capability
• Sector Lock Capabilities, Bootloader Protection, Security Bit
• 32 Fuses, Erased During Chip Erase
• User Page For Data To Be Preserved During Chip Erase
penalty of 1 wait state access
to only 15% compared to 0 wait state operation
Table 5-1 on page
40)
Table 5-1 on page
AT32UC3C
40)
39
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