EVAL-ADF7023-JDB1Z Analog Devices Inc, EVAL-ADF7023-JDB1Z Datasheet - Page 70

• Manufacturer Part Number: EVAL-ADF7023-JDB1Z
• Description: BOARD EVAL ADF7023-JDB1Z
• Manufacturer: Analog Devices Inc
• Series: -r
• Type: Transceiverr

Specifications of EVAL-ADF7023-JDB1Z

• Frequency: 902MHz ~ 958MHz
• Kit Application Type: Wireless Connectivity
• Application Sub Type: RF Transceiver
• Features: Operating At RF Band 902MHz To 958MHz, PC Interface And Control
• Silicon Manufacturer: Analog Devices
• Silicon Core Number: ADF7023
• Kit Contents: Board, Manual
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ADF7023

ADF7023-J
Step 3: Calculate the DISCRIM_PHASE Setting
The phase setting of the discriminator is calculated based on the
Discriminator Coefficient K, as described in Table 37. The phase is
set using the DISCRIM_PHASE[1:0] value in the RADIO_CFG_6
register (Address 0x112).
Table 37. Setting the DISCRIM_PHASE[1:0] Values Based on K
K
Even
Odd
Even
Odd
AFC
The ADF7023-J features an internal real-time automatic frequency
control loop. In receive mode, the control loop automatically
monitors the frequency error during the packet preamble
sequence and adjusts the receiver synthesizer local oscillator using
proportional integral (PI) control. The AFC frequency error
measurement bandwidth is targeted specifically at the packet
preamble sequence (dc free). AFC is supported during
2FSK/GFSK/MSK/GMSK demodulation.
AFC can be configured to lock on detection of the qualified
preamble or on detection of the qualified sync word. To lock
AFC on detection of the qualified preamble, set AFC_LOCK_
MODE = 3 (Address 0x116) and ensure that preamble detection is
enabled in the PREAMBLE_MATCH register (Address 0x11B).
AFC lock is released if the sync word is not detected immediately
after the end of the preamble. In packet mode, if the qualified
preamble is followed by a qualified sync word, the AFC lock is
maintained for the duration of the packet. In sport mode, the
AFC lock is released on transitioning back to the PHY_ON state or
when a CMD_PHY_RX is issued while in the PHY_RX state.
To lock AFC on detection of the qualified sync word, set
AFC_LOCK_MODE = 3 and ensure that preamble detection is
disabled in the PREAMBLE_MATCH register (Address 0x11B). If
this mode is selected, consideration must be given to the selection of
the sync word. The sync word should be dc free and have short run
lengths yet low correlation with the preamble sequence. See the
sync word description in the Packet Mode section for further
details. After lock on detection of the qualified sync word, the AFC
lock is maintained for the duration of the packet. In sport mode,
the AFC lock is released on transitioning back to the PHY_ON state
or when CMD_ PHY_RX is issued while in the PHY_RX state.
AFC is enabled by setting the AFC_LOCK_MODE bits in the
RADIO_CFG_10 register (Address 0x116), as described in Table 38.
Table 38. AFC Mode
AFC_LOCK_MODE [1:0]
0
1
2
3
K/2
Even
Odd
(K + 1)/2
Even
Odd
Mode
Free running: AFC is free running.
Disabled: AFC is disabled.
Hold: AFC is paused.
Lock: AFC locks after the preamble
or sync word.
DISCRIM_PHASE[1:0]
0
1
2
3
Rev. 0 | Page 70 of 100
The bandwidth of the AFC loop can be controlled by the
AFC_KI and AFC_KP bits in the RADIO_CFG_11 register
(Address 0x117).
The maximum AFC pull-in range is automatically set based
on the programmed IF filter bandwidth (the IFBW bits in the
RADIO_CFG_9 register (Address 0x115).
Table 39. Maximum AFC Pull-In Range
IF Bandwidth (kHz)
100
150
200
300
AFC and Preamble Length
The AFC requires a certain number of the received preamble
bits to correct the frequency error between the transmitter and
the receiver. The number of preamble bits required depends on
the data rate and whether the AFC is locked on detection of the
qualified preamble or locked on detection of the qualified sync
word. This is discussed in more detail in the Recommended
Receiver Settings for 2FSK/GFSK/MSK/GMSK section.
AFC Readback
The frequency error between the received carrier and the receiver
local oscillator can be measured when AFC is enabled. The error
value can be read from the FREQUENCY_ERROR_READBACK
register (Address 0x372), where each LSB equates to 1 kHz. The
value is a twos complement number. The FREQUENCY_ERROR_
READBACK value is valid in the PHY_RX state after the AFC
has been locked. The value is retained in the FREQUENCY_
ERROR_READBACK register after recovering a packet and
transitioning back to the PHY_ON state.
Post-Demodulator Filter
A second-order, digital low-pass filter removes excess noise from
the demodulated bit stream at the output of the discriminator. The
bandwidth of this post-demodulator filter is programmable and
must be optimized for the user’s data rate and received modulation
type. If the bandwidth is set too narrow, performance degrades
due to inter-symbol interference (ISI). If the bandwidth is set
too wide, excess noise degrades the performance of the receiver.
For optimum performance, the post-demodulator filter bandwidth
should be set close to 0.75 times the data rate (when using
FSK/GFSK/MSK/GMSK modulation). The actual bandwidth of
the post-demodulator filter is given by
where POST_DEMOD_BW is set in the RADIO_CFG_4
register (Address 0x110).
Post-Demodulator Filter Bandwidth (kHz) =
POST_DEMOD_BW × 2
Max AFC Pull-In Range (kHz)
±50
±75
±100
±150