AN983BX-BG-T-V3 Infineon Technologies, AN983BX-BG-T-V3 Datasheet - Page 43
AN983BX-BG-T-V3
Manufacturer Part Number
AN983BX-BG-T-V3
Description
IC PCI TO ETHERNET LAN 128-PQFP
Manufacturer
Infineon Technologies
Datasheet
1.AN983B-BG-T-V8.pdf
(116 pages)
Specifications of AN983BX-BG-T-V3
Applications
Ethernet Controller
Interface
USB
Voltage - Supply
3 V ~ 3.6 V
Package / Case
128-BFQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AN983BXBGTV3
SP000103413
SP000103413
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AN983BX-BG-T-V3
Manufacturer:
Infineon Technologies
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LT_CR3
Latency Timer
Field
Res
LT
CLS
I/O Base Address
IOBA_CR4
I/O Base Address
Field
IOBA
Res
IOSI
Data Sheet
Bits
31:16
15:8
7:0
Bits
31:8
7:1
0
Type
ro
rw
rw
Type
rw
ro
ro
Registers and Descriptors DescriptionAN983B/BX Configuration Registers
Description
Reserved
Latency Timer
This value specifies the latency timer of the AN983B/BX in units of PCI
bus clock. Once the AN983B/BX asserts FRAME#, the latency timer
starts to count. If the latency timer expires and the AN983B/BX still
asserted FRAME#, then the AN983B/BX will terminate the data
transaction as soon as its GNT# is removed.
Cache Line Size
This value specifies the system cache line size in units of 32-bit double
words (DW). The AN983B/BX supports 8, 16, and 32 DW of cache line
size. This value is used by the AN983B/BX driver to program the cache
alignment bits (bit 14 and 15 of CSR0). The cache alignment bits are used
for cache oriented PCI commands; say memory-read-line, memory-read-
multiple, and memory-write-and-invalidate.
Description
I/O Base Address
This value indicates the base address of PCI control and status register
(CSR0~28).
Reserved
I/O Space Indicator
1
B
, means that the configuration registers map into the I/O space
Offset
Offset
0C
10
43
H
H
Rev. 1.81, 2005-12-15
AN983B/BX
Reset Value
Reset Value
0000 0000
0000 0001
H
H
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