DS2405Z/T&R Maxim Integrated Products, DS2405Z/T&R Datasheet - Page 5

• Manufacturer Part Number: DS2405Z/T&R
• Description: IC SWITCH ADDRESS NCH O-D SOT223
• Manufacturer: Maxim Integrated Products

Specifications of DS2405Z/T&R

• Interface: 1-Wire
• Voltage - Supply: 2.8 V ~ 6 V
• Package / Case: SOT-223 (3 leads + Tab), SC-73, TO-261
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Applications: -

ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of five ROM function commands. All ROM
function commands are 8 bits long. A list of these commands follows (refer to flowchart in Figure 4).
Read ROM [33h]
This command allows the bus master to read the DS2405’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can be used only if there is a single DS2405 on the bus. If more
than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same
time (open drain will produce a wired-AND result).
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific device on a multidrop bus. All devices that do not match the 64-bit ROM sequence will wait for a
Reset Pulse. The DS2405 that exactly matches the 64-bit ROM sequence will toggle the state of its PIO
pin after the 64
on and vice versa. After the last bit of the ROM sequence is received from the bus master and the PIO pin
of the selected DS2405 has toggled, additional read time slots issued by the bus master will cause the
DS2405 to output the logic state of its PIO pin onto the 1-Wire bus. If the pulldown is on and the PIO pin
is a logical 0, the DS2405 will respond with read-0 time slots. If the pulldown is off and the PIO pin is a
logical 1 (external pullup is required), the DS2405 will respond with read-1 time slot. Each additional
read time slot issued by the bus master will continue to indicate the state of the PIO pin until a Reset
Pulse is received from the bus master.
Search ROM [F0h]
When a system is initially interrogated, the bus master may not know the number of devices on the 1-
Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a process
of elimination to identify the 64-bit ROM codes of all slave devices on the bus. This process of
elimination involves repeated application of a simple three-step procedure where the bus master starts by
reading a bit position in the 64-bit ROM, followed by reading the complement of that bit position, and
finally writing to all the devices still involved in the search the desired logic value for that bit position. An
example is shown below and a flowchart for the search algorithm can be found in the “Book of DS19xx
iButton Standards.”
Four devices are connected to the 1-Wire bus. Their binary ROM contents are listed below:
The x’s represent the higher remaining bits. Shown are the lowest 8 bits of the ROM contents. The least
significant bit is to the right in this representation. The search process runs as follows:
1. The master begins the initialization sequence by issuing a Reset Pulse. The devices respond by issuing
2. The master will then issue the Search ROM command on the 1-Wire bus.
Presence Pulses.
th
bit of the match is entered. If the open drain N-channel device was off, it will be turned
device 1: xxxxxx10101100
device 2: xxxxxx01010101
device 3: xxxxxx10101111
device 4: xxxxxx10001000
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