HD64570F Renesas Electronics America, HD64570F Datasheet - Page 301
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HD64570F
Manufacturer Part Number
HD64570F
Description
IC SCA SRL COMM ADAPTER 88QFP
Manufacturer
Renesas Electronics America
Datasheet
1.HD64570F.pdf
(469 pages)
Specifications of HD64570F
Applications
ISDN
Interface
Serial
Voltage - Supply
4.5 V ~ 5.5 V
Package / Case
88-QFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64570F
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
HD64570F16
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64570F16
Manufacturer:
HITACHI/日立
Quantity:
20 000
Company:
Part Number:
HD64570F16V
Manufacturer:
INFINEON
Quantity:
12 000
- Current page: 301 of 469
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6.4.4
Operation: In MSCI-to-memory chained-block transfer mode, frame-bounded data is DMA-
transferred from the MSCI receiver (in bit synchronous mode) to a system memory buffer.
Transfer requests are initiated by the MSCI internal signal. Note that chained-block transfer mode
is not available with the MSCI operated in asynchronous or byte synchronous mode.
MSCI-to-memory transfer employs DMAC channels 0 and 2. For this transfer mode, follow the
steps below starting with the DMA in its initial state. (Steps 1 to 6 may be completed in any
order.)
1.
2.
3.
4.
5.
6.
7.
MSCI-to-memory chained-block transfer mode is shown in figure 6.18.
(CPB). Since the CPB value is fixed during operation, descriptors can be assigned to any
consecutive 64-Kbyte area in system memory.
next to the last receive buffer, into the error descriptor address register (EDA).
receive buffer, into the current descriptor address register (CDA).
shared by all buffers.)
operation.
Specify chained-block transfer mode with the DMA mode register (DMR).
Load the high-order eight bits of the 24-bit descriptor address into the chain pointer base
Load the low-order 16 bits of the start address of the descriptor, which indicates the buffer
Load the low-order 16 bits of the start address of the descriptor, which indicates the first
Load the buffer length in byte units into the receive buffer length (BFL). (This value is
Initialize the chain pointer (CP) and buffer pointer (BP) in each descriptor.
After steps 1 to 6, set the DE bit of the DMA status register (DSR) to 1 to start a DMA
MSCI-to-Memory Chained-Block Transfer Mode
Rev. 0, 07/98, page 285 of 453
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