HD64570F Renesas Electronics America, HD64570F Datasheet - Page 143

• Manufacturer Part Number: HD64570F
• Description: IC SCA SRL COMM ADAPTER 88QFP
• Manufacturer: Renesas Electronics America

Specifications of HD64570F

• Applications: ISDN
• Interface: Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 88-QFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 5.1
Command Name
(Set Value)
TX reset (01H)
TX enable (02H)
TX disable (03H)
TX CRC initialization
(04H)
TX CRC calculation
exclusion (05H)
Transmit Commands
Function
Immediately sets the transmitter to TX disable state (the transmit line goes
to mark): clears the transmit buffer, transmit status in status registers 3–0
(ST3–ST0), and the BRK bit of the control register (CTL).
No other register is affected.
Sets the transmitter to idle state when the transmitter is in TX disable state.
For auto-enable operation, see the description of the AUTO bit in section
5.2.1, MSCI Mode Register 0 (MD0).
Immediately sets the TXRDY bit of MSCI status register 0 to stop the CPU
or DMAC writing data into the transmit buffer. The transmitter enters the TX
disable state after sending the transmit buffer data.
In byte or bit synchronous mode, after sending the transmit buffer data, the
transmitter first enters the underrun state, then enters the idle state
according to the sequence specified by the UDRNC bit of the MSCI control
register and the CRCCC bit of MSCI mode register 0. Finally, the
transmitter enters the TX disable state after a one-bit idle state.
Initializes the transmitter CRC calculator as specified by the CRC0 bit of
MD0 when the first transmit character is transferred to the transmit shift
register after this command is issued.
This command is used in byte or bit synchronous mode.
Excludes one specific character from the transmit CRC calculation.
This command is valid only for the first character transferred to the transmit
shift register after this command is issued. To exclude the first character,
issue the command during transmission of the SYN character preceding
the character to be excluded. (If SYN character transmission timing is not
explicit, write a SYN character to the TX/RX buffer register (TRB) before
the first character, and then issue the command during the SYN character
transmission.)
Command operation is not guaranteed in modes other than byte
synchronous mode.
Rev. 0, 07/98, page 127 of 453