W83627EG Nuvoton Technology Corporation of America, W83627EG Datasheet - Page 101

• Manufacturer Part Number: W83627EG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627EG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CR 27h. (Reserved)
CR 28h. (Global Option; Default 50h)
CR 29h. (OVT#/HM_SMI#, UART A, Game port & MIDI pin select; Default 04h)
6~5
2~0
5~4
2~1
BIT
BIT
7
4
3
7
6
3
0
Reserved.
Reserved.
Reserved.
READ / WRITE
READ / WRITE
R / W
R / W
R / W
R / W
R / W
R / W
R / W
R / W
Flash ROM size select
= 00
= 01
= 10
= 11
Select to enable/disable decoding of BIOS ROM range 000E xxxxh.
= 0
= 1
Select to enable/disable decoding of BIOS ROM range FFFE xxxxh.
= 0
= 1
PRTMODS2 ~ 0 =>
= 0xx
= 1xx
PIN5 function select
= 0
= 1
PIN49~54,56~57 function select
= 0
= 1
PIN119~120 function select
PIN121~128 function select
= 0
= 1
Bit-2
0
0
1
1M
2M
4M (Default)
8M
Enable decoding of BIOS ROM range at 000E xxxxh.
Disable decoding of BIOS ROM range at 000E xxxxh.
Enable decoding of BIOS ROM range at FFFE xxxxh.
Disable decoding of BIOS ROM range at FFFE xxxxh.
Parallel Port Mode.
Reserved.
PIN5
PIN5
PIN49~54,56~57
PIN49~54,56~57
PIN121~128
PIN121~128
W83627EHF/EF, W83627EHG/EG
Bit-1
0
1
x
OVT#
HM_SMI#.
- 95 -
Game Port.
GPIO1.
PIN 119~120
PIN 119~120
PIN 119~120
UART A.
GPIO6.
DESCRIPTION
DESCRIPTION
PIN119~PIN120 function
CPUFANIN1, CPUFANOUT1
GP21, GP20
MSI, MSO
Publication Release Date: Nov. 2006
(Default)
Revision 1.3