UJA1065TW/5V0,518 NXP Semiconductors, UJA1065TW/5V0,518 Datasheet - Page 23
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UJA1065TW/5V0,518
Manufacturer Part Number
UJA1065TW/5V0,518
Description
IC CAN/LIN FAIL-SAFE 32HTSSOP
Manufacturer
NXP Semiconductors
Datasheet
1.UJA1065TW3V3CT.pdf
(76 pages)
Specifications of UJA1065TW/5V0,518
Package / Case
32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
Applications
Networking
Interface
CAN, LIN
Voltage - Supply
5.5 V ~ 52 V
Mounting Type
Surface Mount
Product
Controller Area Network (CAN)
Number Of Transceivers
1
Data Rate
20 Kbps
Supply Voltage (max)
27 V, 52 V
Supply Voltage (min)
5.5 V
Supply Current (max)
10 mA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4374-2
935281292518
UJA1065TW/5V0-T
UJA1065TW/5V0-T
935281292518
UJA1065TW/5V0-T
UJA1065TW/5V0-T
NXP Semiconductors
UJA1065_7
Product data sheet
6.7.4.3 GND shift detection
6.8.1.1 Active mode
6.8.1 Mode control
6.8 LIN transceiver
The SBC can detect ground shifts in reference to the CAN-bus. Two different ground shift
detection levels can be selected with the GSTHC bit in the Configuration register. The
failure can be read out in the System Diagnosis register. Any detected or recovered GND
shift event is signalled with an interrupt, if enabled.
The integrated LIN transceiver of the UJA1065 is a LIN 2.0 compliant transceiver. The
transceiver has the following features:
The controller of the LIN transceiver provides two modes of operation: Active mode and
Off-line mode; see
consume current, but wake-up events will be recognized by the separate wake-up
receiver.
In Active mode the LIN transceiver can transmit data to and receive data from the LIN bus.
To enter Active mode the LMC bit must be set in the Physical Layer Control register and
the SBC must be in Normal mode or Flash mode.
Fig 10. States LIN transceiver
•
•
•
SAE J2602 compliant and compatible with LIN revision 1.3
Fail-safe LIN termination to BAT42 via dedicated RTLIN pin
Enhanced error handling and reporting of bus and TXD failures; these failures are
separately identified in the System Diagnosis register
Figure
power-on
Normal or Flash mode
Rev. 07 — 25 February 2010
AND LMC = 1
SBC enters
10. In Off-line mode the transmitter and receiver do not
transmitter: ON/OFF (LTC)
RXDL: wake-up status
RTLIN: 75 μA/OFF
RTLIN: ON/75 μA
receiver: wake-up
RXDL: bitstream
transmitter: OFF
Off-line mode
Active mode
receiver: ON
High-speed CAN/LIN fail-safe system basis chip
Restart or Fail-safe mode
Stand-by, Start-up,
OR LMC = 0
SBC enters
Fail-safe mode
SBC enters
001aad184
UJA1065
© NXP B.V. 2010. All rights reserved.
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