UJA1065TW/3V0,518 NXP Semiconductors, UJA1065TW/3V0,518 Datasheet - Page 10
![IC CAN/LIN FAIL-SAFE 32HTSSOP](/photos/6/94/69422/uja1065_hq_sml.jpg)
UJA1065TW/3V0,518
Manufacturer Part Number
UJA1065TW/3V0,518
Description
IC CAN/LIN FAIL-SAFE 32HTSSOP
Manufacturer
NXP Semiconductors
Datasheet
1.UJA1065TW3V3CT.pdf
(76 pages)
Specifications of UJA1065TW/3V0,518
Package / Case
32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
Applications
Networking
Interface
CAN, LIN
Voltage - Supply
5.5 V ~ 52 V
Mounting Type
Surface Mount
Product
Controller Area Network (CAN)
Number Of Transceivers
1
Data Rate
20 Kbps
Supply Voltage (max)
27 V, 52 V
Supply Voltage (min)
5.5 V
Supply Current (max)
10 mA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4372-2
935281289518
UJA1065TW/3V0-T
UJA1065TW/3V0-T
935281289518
UJA1065TW/3V0-T
UJA1065TW/3V0-T
NXP Semiconductors
UJA1065_7
Product data sheet
6.2.5 Standby mode
Entering Normal mode does not activate the CAN or LIN transceiver automatically. The
CAN Mode Control (CMC) bit must be used to activate the CAN medium if required,
allowing local cyclic wake-up scenarios to be implemented without affecting the CAN-bus.
The LIN Mode Control (LMC) bit must be used to activate the LIN medium if required,
allowing local cyclic wake-up scenarios to be implemented without affecting the LIN-bus.
In Standby mode the system is set into a state with reduced current consumption.
Entering Standby mode overrides the CMC bit, allowing the CAN transceiver to enter the
low-power mode autonomously. The watchdog will, however, continue to monitor the
microcontroller (Time-out mode) since it is powered via pin V1.
In the event that the host microcontroller can provide a low-power mode with reduced
current consumption in its Standby mode or Stop mode, the watchdog can be switched off
entirely in Standby mode of the SBC. The SBC monitors the microcontroller supply current
to ensure that there is no unobserved phase with disabled watchdog and running
microcontroller. The watchdog will remain active until the supply current drops below
I
Should the current increase to I
application specific hardware, the watchdog will start operating again with the previously
used time-out period. If the watchdog is not triggered correctly, a system reset will occur
and the SBC will enter Start-up mode.
If Standby mode is entered from Normal mode with the selected watchdog OFF option,
the watchdog will use the maximum time-out as defined for Standby mode until the supply
current drops below the current detection threshold; the watchdog is now OFF. If the
current increases again, the watchdog is immediately activated, again using the maximum
watchdog time-out period. If the watchdog OFF option is selected during Standby mode,
the last used watchdog period will define the time for the supply current to fall below the
current detection threshold. This allows the user to align the current supervisor function to
the application needs.
Generally, the microcontroller can be activated from Standby mode via a system reset or
via an interrupt without reset. This allows implementation of differentiated start-up
behavior from Standby mode, depending on the application needs:
thL(V1)
•
•
If the watchdog is still running during Standby mode, the watchdog can be used for
cyclic wake-up behavior of the system. A dedicated Watchdog Time-out Interrupt
Enable (WTIE) bit enables the microcontroller to decide whether to receive an
interrupt or a hardware reset upon overflow. The interrupt option will be cleared in
hardware automatically with each watchdog overflow to ensure that a failing main
routine is detected while the interrupt service still operates. So the application
software must set the interrupt behavior each time before a standby cycle is entered.
Any wake-up via the CAN-bus or the LIN-bus together with a local wake-up event will
force a system reset event or an interrupt to the microcontroller. So it is possible to
exit Standby mode without any system reset if required.
. Below this current limit the watchdog is disabled.
Rev. 07 — 25 February 2010
thH(V1)
, e.g. as result of a microcontroller wake-up from
High-speed CAN/LIN fail-safe system basis chip
UJA1065
© NXP B.V. 2010. All rights reserved.
10 of 76