PX1012AI-EL1/G,551 NXP Semiconductors, PX1012AI-EL1/G,551 Datasheet

PCI-EXPRESS X1 PHY 81-LFBGA

PX1012AI-EL1/G,551

Manufacturer Part Number
PX1012AI-EL1/G,551
Description
PCI-EXPRESS X1 PHY 81-LFBGA
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PX1012AI-EL1/G,551

Applications
PCI Express MAX to PCI Express PHY
Interface
IEEE 1149.1
Voltage - Supply
1.2 V
Package / Case
81-LFBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3617
935282112551
PX1012AI-EL1/G-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PX1012AI-EL1/G,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
1. General description
2. Features
2.1 PCI Express interface
2.2 PHY/MAC interface
The PX1011A/PX1012A is a high-performance, low-power, single-lane PCI Express
electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and
signaling. The PX1011A/1012A PCI Express PHY is compliant to the PCI Express Base
Specification, Rev. 1.0a , and Rev. 1.1 . The PX1011A/1012A includes features such as
clock and data recovery (CDR), data serialization and de-serialization, 8b/10b encoding,
analog buffers, elastic buffer and receiver detection, and provides superior performance to
the Media Access Control (MAC) layer devices.
The PX1011A/1012A is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface.
Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE)
specification, enhanced and adapted for off-chip applications with the introduction of a
source synchronous clock for transmit and receive data. The 8-bit data interface operates
at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O
interfaces available in FPGA products.
The PX1011A/1012A PCI Express PHY supports advanced power management
functions. The PX1011AI/PX1012AI is for the industrial temperature range ( 40 C to
+85 C).
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PX1011A/PX1012A
PCI Express stand-alone X1 PHY
Rev. 02 — 18 May 2006
Compliant to PCI Express Base Specification 1.1
Single PCI Express 2.5 Gbit/s lane
Data and clock recovery from serial stream
Serializer and De-serializer (SerDes)
Receiver detection
8b/10b coding and decoding, elastic buffer and word alignment
Supports loopback
Supports direct disparity control for use in transmitting compliance pattern
Supports lane polarity inversion
Low jitter and Bit Error Rate (BER)
Based on Intel PHY Interface for PCI Express architecture v1.0 (PIPE)
Adapted for off-chip with additional synchronous clock signals (PXPIPE)
8-bit parallel data interface for transmit and receive at 250 MHz
2.5 V SSTL_2 class I signaling
Product data sheet

Related parts for PX1012AI-EL1/G,551

PX1012AI-EL1/G,551 Summary of contents

Page 1

... The 8-bit data interface operates at 250 MHz with SSTL_2 signaling. The SSTL_2 signaling is compatible with the I/O interfaces available in FPGA products. The PX1011A/1012A PCI Express PHY supports advanced power management functions. The PX1011AI/PX1012AI is for the industrial temperature range ( +85 C). 2. Features 2.1 PCI Express interface I Compliant to PCI Express Base Specifi ...

Page 2

Philips Semiconductors 2.3 JTAG interface I JTAG (IEEE 1149.1) boundary scan interface I Built-In Self Test (BIST) controller tests SerDes and I/O blocks at speed I 3.3 V CMOS signaling 2.4 Power management I Dissipates < 300 ...

Page 3

... Ordering information Type number Solder process PX1011A-EL1 SnPb solder ball compound PX1011A-EL1/G Pb-free (SnAgCu solder ball compound) PX1011AI-EL1/G Pb-free (SnAgCu solder ball compound) PX1012A-EL1/G Pb-free (SnAgCu solder ball compound) PX1012AI-EL1/G Pb-free (SnAgCu solder ball compound) 5. Marking Table 3. Line Table 4. Line [1] Industrial temperature range. ...

Page 4

Philips Semiconductors 6. Block diagram Fig 1. Block diagram PX1011A_PX1012A_2 Product data sheet TXDATA [ 7:0 ] TXCLK RXCLK Ln_TxData0 Ln_TxData1 8b/10b ENCODE PARALLEL TO SERIAL 250 MHz clock CLK GENERATOR TX I/O REFCLK I/O TX_P TX_N REFCLK_P REFCLK_N Rev. ...

Page 5

... RXIDLE SS REFCLK_P REFCLK_N RX_P RX_N TX_P TX_N J VREFS Transparent top view. Fig 3. Ball mapping PX1011A_PX1012A_2 Product data sheet PX1011A-EL1 PX1011A-EL1/G PX1011AI-EL1/G PX1012A-EL1/G ball A1 PX1012AI-EL1/G index area Transparent top view RXDATA6 RXDATA4 RXDATA3 RXDATA7 RXDATA5 DDD2 SS DDD2 DDA2 DDA1 V TMS V DDD1 DDD1 ...

Page 6

Philips Semiconductors 7.2 Pin description The PHY input and output pins are described in output is defined from the perspective of the PHY. Thus a signal on a pin described as an output is driven by the PHY and a ...

Page 7

Philips Semiconductors Table 9. Symbol RXVALID PHYSTATUS RXIDLE RXSTATUS0 RXSTATUS1 RXSTATUS2 Table 10. Symbol TXCLK RXCLK REFCLK_P REFCLK_N PVT VREFS Table 11. Symbol TMS TRST_N TCK TDI TDO PX1011A_PX1012A_2 Product data sheet PXPIPE interface status signals Pin Type Signaling C8 ...

Page 8

Philips Semiconductors Table 12. Symbol V DDA1 V DDA2 V DDD1 V DDD2 V DDD3 Functional description The main function of the PHY is to convert digital data into electrical signals and vice versa. The ...

Page 9

Philips Semiconductors The de-serializer or Serial-to-Parallel converter (S2P) de-serializes this data into 10-bits parallel data. Since the S2P has no knowledge about the data, the word alignment is still random. This is fixed in the digital domain by the PCS ...

Page 10

Philips Semiconductors RESET_N PHYSTATUS Fig 4. Reset 8.5 Power management The power management signals allow the PHY to manage power consumption. The PHY meets all timing constraints provided in the PCI Express base specification regarding clock recovery and link training ...

Page 11

Philips Semiconductors Table 13. Summary of power management state PWRDWN[1:0] Power management state 00b P0, normal operation 01b P0s, power saving state 10b P1, lower power state 11b illegal, PHY will enter P1 [1] TXIDLE = 0 [2] TXIDLE = ...

Page 12

Philips Semiconductors • The PHY continues to provide the received data on the PXPIPE interface, behaving exactly like normal data reception. • The PHY transitions from normal transmission of data from the PXPIPE interface to looping back the received data ...

Page 13

Philips Semiconductors RXDATA[7:0] RXDET_LOOPB TX_P, TX_N Fig 7. Loopback end 8.8 Electrical idle The PCI Express Base Specification requires that devices send an Electrical Idle ordered-set before TX goes to the electrical idle state. The timing diagram of TXCLK TXDATA[7:0] ...

Page 14

Philips Semiconductors Table 14 Table 14. PWRDWN[1:0] P0: 00b P0s: 01b P1: 10b 8.9 Clock tolerance compensation The PHY receiver contains an elastic buffer used to compensate for differences in frequencies between bit rates at the two ends of a ...

Page 15

Philips Semiconductors RXDATA[7:0] RXSTATUS2, RXSTATUS1, RXSTATUS0 Fig 10. Clock correction - remove a SKP 8.10 Error detection The PHY is responsible for detecting receive errors of several types. These errors are signaled to the MAC layer using the receiver status ...

Page 16

Philips Semiconductors 8.10.1 8b/10b decode errors For a detected 8b/10b decode error, the PHY places an EDB (EnD Bad) symbol in the data stream in place of the bad byte, and encodes RXSTATUS with a decode error during the clock ...

Page 17

Philips Semiconductors RXDATA[7:0] RXSTATUS2, RXSTATUS1, RXSTATUS0 Fig 13. Elastic buffer underflow For an elastic buffer overflow, the overflow is signaled during the clock cycle where the dropped symbol would have appeared in the data stream. In the timing diagram of ...

Page 18

Philips Semiconductors 8.12 Setting negative disparity To set the running disparity to negative, the MAC asserts TXCOMP for one clock cycle that matches with the data that transmitted with negative disparity. TXDATA[7:0] TX_P, TX_N Fig 16. Setting ...

Page 19

Philips Semiconductors 9. Limiting values Table 16. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol V DDD1 V DDD2 V DDD3 DDA1 V DDA2 V esd T stg amb [1] Human ...

Page 20

Philips Semiconductors 11. Characteristics Table 18. PCI Express PHY characteristics Symbol Parameter Supplies V digital supply voltage 1 DDD1 V digital supply voltage 2 DDD2 V digital supply voltage 3 DDD3 V supply voltage DD V analog supply voltage 1 ...

Page 21

Philips Semiconductors Table 18. PCI Express PHY characteristics Symbol Parameter Transmitter UI unit interval V differential peak-to-peak output voltage TX_DIFFp-p t maximum time between the jitter median and TX_EYE_m-mJITTER maximum deviation from the median t maximum transmitter jitter time TX_JITTER_MAX ...

Page 22

Philips Semiconductors Table 19. PXPIPE characteristics Symbol Parameter f RXCLK frequency RXCLK f TXCLK frequency TXCLK V voltage on pin VREFS VREFS V SSTL_2 HIGH-level output voltage OH(SSTL2) V SSTL_2 LOW-level output voltage OL(SSTL2) V SSTL_2 HIGH-level input voltage IH(SSTL2) ...

Page 23

Philips Semiconductors differential Fig 18. Transition eye Fig 19. Non transition eye PX1011A_PX1012A_2 Product data sheet 0.6 0.5 0.4 signal (V) 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.2 0.1 0 0.1 0 ...

Page 24

Philips Semiconductors 12. Package outline LFBGA81: plastic low profile fine-pitch ball grid array package; 81 balls; body 1.05 mm ball A1 index area ball A1 index ...

Page 25

Philips Semiconductors 13. Soldering 13.1 Introduction to soldering surface mount packages There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not ...

Page 26

Philips Semiconductors – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to ...

Page 27

Philips Semiconductors [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C body ...

Page 28

... T – added industrial temperature range • Table 2 “Ordering PX1012A-EL1/G; added industrial temperature range Type numbers PX1011AI-EL1 and PX1012AI-EL1; added column “Soldering compound” • Figure 1 “Block diagram” • Table – title changed from “Marking” to “Leaded package marking” ...

Page 29

Philips Semiconductors Table 24. Revision history …continued Document ID Release date PX1011A_PX1012A_2 20060518 • Modifications: (continued) Table 8 “PXPIPE interface command RXDET_LOOPB, TXIDLE, TXCOMP, and RXPOL • Table 9 “PXPIPE interface status • Table 10 “Clock and reference • Table ...

Page 30

Philips Semiconductors Table 24. Revision history …continued Document ID Release date PX1011A_PX1012A_2 20060518 • Modifications: (continued) Section 8.10 “Error – 1st paragraph, 2nd sentence: changed “signals (RXSTATIS2 to RXSTATUS0).” to – 2nd paragraph: changed from “... at the point in ...

Page 31

Philips Semiconductors 17. Legal information 17.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

Page 32

Philips Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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