DS33M33N+ Maxim Integrated Products, DS33M33N+ Datasheet - Page 15

• Manufacturer Part Number: DS33M33N+
• Description: IC MAPPER ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33M33N+

• Applications: Data Transport
• Interface: SPI
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.2 PDH VCAT/LCAS
1.6
1.6.1 GFP-F Encapsulation (per ITU-T G.7041)
1.6.2 HDLC Encapsulation
1.6.3 cHDLC Encapsulation
1.6.4 X.86 Encapsulation Support
1.7
Rev: 111908
___________________________________________________ DS33M30/M31/M33 ABRIDGED DATA SHEET
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Supports up to three DS3/E3 in one VCG (per ITU-T G.7043/G.7042)
Supports differential delay compensation up to 200ms
Encapsulation
Up to three encap/decap engines for various port configurations
GFP-F idle frame insertion and extraction
Null header support
cHEC-based frame delineation
X
Barker sequence scrambling and descrambling
Supports CSF frame handling
CRC-32 generation and verification
Programmable 16/32-bit FCS insertion/extraction
Support for bit and byte stuffed operation
Programmable address/control/PID fields
Self-synchronizing X
Valid and invalid frame counters
Programmable inter-frame fill
Frame filtering of FCS errors
cHDLC support with SLARP extraction
Bit stuffing with address/control/PID/FCS fields
Programmable interframe fill length
Transparency processing
Counters: number of received valid frames and erred frames
Incoming frame discard due to FCS error, abort, or frame length longer than preset max
Default maximum frame length is associated with the maximum PDU length of MAC frame
Extract SLARP for external processor interpretation
Transmit Transparency Processing
Receive rate adaptation removal
Selectable X
Valid and Invalid Frame counters
Frame filtering of FCS errors
Ethernet Feature Overview
Supports Single 10/100/1000Mbps Ethernet interfaces (Half or Full Duplex)
WAN Packet field modifications (Header and FCS)
Byte stuffed HDLC or GFP (Null or Linear) for any valid BW and VCG size
Ethernet Frame modifications (Remove 14/18, VLAN/Q-in-Q and Ethernet FCS)
LAN Frame Inspection for VLAN (Forwarding, Discarding, Extract), Extract, Priority Coding
WAN Frame Inspection for VLAN (Forwarding, Extract), Extract
Scheduler with options of strict priority or WRR
Up to 200ms of differential delay using external DDR SDRAM
Bridge Filtering for 10/100Mbps applications
Policing based on per-port, per-COS, or per-multicast/broadcast type
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+1 payload scrambling and descrambling
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+1 packet scrambling
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+1 packet scrambling
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