MT8VDDT6464HDY-40BJ1 Micron Technology Inc, MT8VDDT6464HDY-40BJ1 Datasheet - Page 21
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MT8VDDT6464HDY-40BJ1
Manufacturer Part Number
MT8VDDT6464HDY-40BJ1
Description
MODULE DDR SDRAM 512MB 200SODIMM
Manufacturer
Micron Technology Inc
Series
-r
Specifications of MT8VDDT6464HDY-40BJ1
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
400MT/s
Features
-
Package / Case
200-SODIMM
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
pdf: 09005aef80867ab3, source: 09005aef80867a99
DD8C16_32_64x64AG.fm - Rev. G 9/04 EN
31. READs and WRITEs with auto precharge are not
32. Any positive glitch in the nominal voltage must be
33. Normal Output Drive Curves:
160
140
120
100
80
60
40
20
Figure 9: Pull-Down Characteristics
0
0.0
allowed to be issued until
fied prior to the internal precharge command
being issued.
less than 1/3 of the clock and not more than
+400mV or 2.9V, whichever is less. Any negative
glitch must be less than 1/3 of the clock cycle and
not exceed either -300mV or 2.2V, whichever is
more positive.
d. The variation in driver pull-up current within
a. The full variation in driver pull-down current
b. The variation in driver pull-down current
c. The full variation in driver pull-up current
e. The full variation in the ratio of the maximum
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9,
Pull-Down Characteristics.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 9, Pull-Down Characteristics.
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 10,
Pull-Up Characteristics.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
10, Pull-Up Characteristics.
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
0.5
1.0
V
V
OUT
OUT
(V)
(V)
t
RAS(min) can be satis-
1.5
2.0
Minimum
2.5
21
34. The voltage levels used are derived from a mini-
35. V
36. V
37.
38.
39. During initialization, V
40. The current Micron part operates below the slow-
41. For the -335, -262, -26A and -265 modules, I
42. Random addressing changing and 50 percent of
128MB, 256MB, 512MB (x64, SR)
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
Figure 10: Pull-Up Characteristics
0.0
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
width ≤ 3ns and the pulse width cannot be greater
than 1/3 of the cycle rate. V
(MIN) = -1.5V for a pulse width ≤ 3ns and the
pulse width cannot be greater than 1/3 of the
cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
be equal to or less than V
V
even if V
42Ω of series resistance is used between the V
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
is specified to be 35mA per DDR SDRAM device at
100 MHz.
data changing at every transfer.
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and
f. The full variation in the ratio of the nominal
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
DD
RPST), or begins driving (
TT
184-PIN DDR SDRAM UDIMM
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
overshoot: V
and V
may be 1.35V maximum during power up,
t
DQSCK (MIN) +
DD
DD
0.5
DD
level and the referenced test load. In
/V
Q must track each other.
DD
Q are 0V, provided a minimum of
IH
(
1.0
MAX
V
DD
t
Q - V
RPRE (MAX) condition.
t
RPRE begin point are not
) = V
DD
OUT
DD
t
Q, V
t
LZ (MIN) will prevail
(V)
RPRE).
DD
1.5
+ 0.3V. Alternatively,
Q + 1.5V for a pulse
IL
TT
t
DQSCK (MAX) +
, and V
undershoot: V
©2004 Micron Technology. Inc.
2.0
REF
DD
must
3N
TT
2.5
IL