SEG01G72A1BH1MT-37R Swissbit NA Inc, SEG01G72A1BH1MT-37R Datasheet - Page 7

• Manufacturer Part Number: SEG01G72A1BH1MT-37R
• Description: DRAM DDR2 1GB 200-SORDIMM W/ECC
• Manufacturer: Swissbit NA Inc
• Series: -r

Specifications of SEG01G72A1BH1MT-37R

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 533MHz
• Features: -
• Package / Case: 200-SORDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1043

I
(0°C ≤ T
Swissbit
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
DD
Parameter
& Test Condition
OPERATING CURRENT *) :
One device bank Active-Precharge;
t
between valid commands;
DQ inputs changing once per clock cycle; Address and control
inputs changing once every two clock cycles
OPERATING CURRENT *) :
One device bank; Active-Read-Precharge;
I
t
t
commands; Address inputs changing once every two clock
cycles; Data Pattern is same as I
PRECHARGE POWER-DOWN CURRENT:
All device banks idle; Power-down mode;
t
are not changing; DQ’s are floating at V
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
t
All Control and Address bus inputs are not changing; DQ’s are
floating at V
PRECHARGE STANDBY CURRENT:
All device banks idle;
t
All other Control and Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per clock
cycle
ACTIVE POWER-DOWN
CURRENT:
All device banks open; t
(I
Address bus inputs are not
changing; DQ’s are floating at
V
ACTIVE STANDBY CURRENT:
All device banks open; t
t
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per clock
cycle
OPERATING READ CURRENT:
All device banks open, Continuous burst reads; One module
rank active; I
(I
HIGH between valid commands; Address bus inputs are
changing once every two clock cycles; DQ inputs changing
once per clock cycle
RC
OUT
CK
RCD
CK
CK
CK
RAS
DD
REF
DD
Specifications and Conditions
= t
); CKE is LOW; All Control and
), t
= t
= t
= t
= t
= 0mA; BL = 4, CL = CL (I
= t
= t
RC
RAS
CK
CK
CK
CK
CASE
RAS
RCD
(I
(I
(I
(I
(I
DD
= t
DD
DD
DD
DD
MAX (I
(I
≤ + 85°C; V
); t
REF
DD
), t
); CKE is LOW; All Control and Address bus inputs
); CKE is HIGH, CS# is HIGH;
); CKE is HIGH, CS# is HIGH;
RAS
OUT
CK
); CKE is HIGH, CS# is HIGH between valid
RC
MAX (I
= 0mA; BL = 4, CL = CL (I
= t
= t
DD
RC
), t
CK
DDQ
(I
(I
RP
DD
DD
DD
CK
CK
= t
), t
= +1.8V ± 0.1V, V
); CKE is HIGH, CS# is HIGH
), t
= t
= t
RP
RP
RAS
CK
CK
(I
DD
= t
DD
= t
(I
), AL = 0;
DD4W
RP
DD
);
RAS
Fon: [phone]
Fax: [phone]
),
(I
Fast PDN Exit
MR[12] = 0
Slow PDN Exit
MR[12] = 1
DD
MIN (I
); CKE is HIGH, CS# is
REF
DD
DD
= +1.8V ± 0.1V)
DD
), AL = 0; t
),
Data Sheet
CK
= t
CK
www.swissbit.com
eMail: [e-mail]
Symbol
I
I
I
I
I
I
I
I
DD0
DD1
DD2P
DD2Q
DD2N
DD3P
DD3N
DD4R
4200-444
1188
max.
693
918
126
720
720
540
180
900
Rev.1.0
5300-555
1278
max.
828
963
126
720
720
540
180
990
30.07.2010
Page 7
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