SEG01G72A1BH1MT-37R Swissbit NA Inc, SEG01G72A1BH1MT-37R Datasheet - Page 11

• Manufacturer Part Number: SEG01G72A1BH1MT-37R
• Description: DRAM DDR2 1GB 200-SORDIMM W/ECC
• Manufacturer: Swissbit NA Inc
• Series: -r

Specifications of SEG01G72A1BH1MT-37R

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 533MHz
• Features: -
• Package / Case: 200-SORDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1043

DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ T
AC CHARACTERISTICS
ODT power-down exit latency
ODT enable from MRS
command
Exit active power-down to READ
command, MR [bit 12 = 0]
Exit active power-down to READ
command, MR [bit 12 = 1]
Exit precharge power-down to
any non-READ command
CKE minimum high/low time
Register Specifications
Parameter
DC high-level
input voltage
DC low-level
input voltage
AC high-level
input voltage
AC low-level
input voltage
Output high voltage
Output low voltage
Input current
Static standby
Static operating
Dynamic operating
(clock tree)
Dynamic operating
(per each input)
Input capacitance
(per device, per pin)
Input capacitance
(per device, per pin)
Notes: 1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR2
Swissbit
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
PARAMETER
CASE
SDRAM registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the
module. Detailed information for this register is available in JEDEC standard JESD82.
≤ + 85°C; V
DD
Q = +1.8V ± 0.1V, V
Symbol Pins
V
V
V
V
V
V
I
I
I
I
I
C
C
I
DD
DD
DDD
DDD
IH
IL
IH
IL
OH
OL
I
I
(
(
(
(
DC
AC
DC
AC
SYMBOL
t
T
t
t
t
t
AXPD
XARD
XARDS
XP
CKE
)
)
)
)
MOD
Fon: [phone]
Fax: [phone]
Address,
control,
command
Address,
control,
command
Address,
control,
command
Address,
control,
command
Parity
output
Parity
output
All pins
All pins
All pins
n/a
n/a
Data
RESET#
DD
6 – AL
= +1.8V ± 0.1V)
MIN
12
8
2
2
3
RESET# = V
V
RESET# = V
V
switching 50% duty cycle;
One data input switching at
Data Sheet
4200-444
IL
IL
(
(
switching 50% duty cycle
RESET# = V
AC
AC
V
t
CK/2
), I
), I
V
I
V
V
RESET# = V
= V
I
I
I
MAX
O
O
= V
= V
= V
V
, 50% duty cycle
Conditions
= 0; CK and CK#
= 0; CK and CK#
IH
DD
SSTL_18
SSTL_18
SSTL_18
SSTL_18
LVCMOS
LVCMOS
DD
REF
DD
(
DD
DD
I
AC
Q = 1.8V
O
Q or V
Q or V
, V
, V
= 0
) or V
SS
±250mV;
I
I
Q (I
7 – AL
= V
= V
SS
MIN
www.swissbit.com
eMail: [e-mail]
12
SS
IL
SS
8
2
2
3
Q;
O
IH
IH
(
DC
Q
Q
5300-555
= 0)
(
(
AC
AC
)
) or
) or
MAX
Min
V
V
REF
REF
125
250
1.2
2.5
-5
0
0
(
(
-
-
-
-
-
-
DC
DC
Unit
Rev.1.0
t
t
t
t
t
ns
CK
CK
CK
CK
CK
) +
) +
V
V
Max
manufacturer
manufacturer
manufacturer
V
REF
REF
Varies by
Varies by
Varies by
DD
(
(
Q + 250
V
100
0.5
3.5
DC
DC
+5
40
DD
-
) - 125
) - 250
30.07.2010
Units
Page 11
mV
mV
mV
mV
mA
µA
µA
µA
µA
pF
pF
V
V
of 14