A5974ADTR STMicroelectronics, A5974ADTR Datasheet - Page 40

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A5974ADTR

Manufacturer Part Number
A5974ADTR
Description
IC REG SW STEP-DOWN 2A 8SOIC
Manufacturer
STMicroelectronics
Series
-r
Type
Step-Down (Buck), PWMr
Datasheet

Specifications of A5974ADTR

Internal Switch(s)
Yes
Synchronous Rectifier
No
Number Of Outputs
1
Voltage - Output
1.235 V ~ 35 V
Current - Output
2A
Frequency - Switching
500kHz
Voltage - Input
4 V ~ 36 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width) Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-11423-2
Application information
8.9
8.10
40/49
As a consequence, the maximum output current is:
Equation 46
where I
Figure 28
driving (350 mA). To implement a boost conversion the LED string must be composed of a
minimum device number having a total voltage drop larger than maximum input voltage.
The input voltage can be either DC or AC thanks to the input bridge rectifier. In the case of a
DC voltage source D1, D2, D3, D4, C1, and C2 can be removed from the circuit and 1
capacitor value can be used for C5.
Synchronization example
See
Figure 29. Synchronization example
Compensation network with MLCC at the output
The A5974AD standard compensation network (please refer to
introduces a single zero and a low frequency pole in the system bandwidth, so a high ESR
output capacitor must be selected to compensate the 180-degree phase shift given by the
LC double pole.
The selection of the output capacitor must guarantee that the zero introduced by this
component is inside the designed system bandwidth and close to the frequency of the
double pole introduced by the LC filter. A general rule for the selection of this compound for
the system stability is provided in
Equation 47
Section 5.3
SW MAX
shows a tested circuit to implement a boost current source for high current LED
represents the rated current of the device.
for details.
f
Z ESR
Doc ID 018762 Rev 1
A5974AD
I
=
Equation
OUT MAX
----------------------------------------------- -
2 π ESR C
f
LC
<
f
Z ESR
1
I
47.
SW MAX
<
OUT
10 f
(
<
1 D
LC
bandwidth
)
Figure 1
A5974AD
and
Section
A5974AD
AM09655v1
7)
μ
F

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