AOZ1037PI Alpha & Omega Semiconductor Inc, AOZ1037PI Datasheet - Page 11

• Manufacturer Part Number: AOZ1037PI
• Description: IC BUCK SYNC ADJ 5A SO8
• Manufacturer: Alpha & Omega Semiconductor Inc
• Series: EZBuck™r
• Type: Step-Down (Buck), PWM - Current Moder

Specifications of AOZ1037PI

• Featured Product: The AOZ103x Family Synchronous Buck Regulator
• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 V ~ 18 V
• Current - Output: 5A
• Frequency - Switching: 500kHz
• Voltage - Input: 4.5 V ~ 18 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width) Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 785-1256-2

where;
f
f
V
G
A/V, and
G
A/V
The compensation capacitor C
make a zero. This zero is put somewhere close to the
dominate pole f
crossover frequency. C
The above equation can be simplified to:
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
Thermal Management and Layout
Consideration
In the AOZ1037 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the V
pins, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the low-side NMOSFET.
Current flows in the second loop when the low-side
NMOSFET is on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input
capacitor, output capacitor, and PGND pin of the
AOZ1037.
In the AOZ1037 buck regulator circuit, the major power
dissipating components are the AOZ1037 and the output
inductor. The total power dissipation of converter circuit
can be measured by input power minus output power.
C
C
C
C
P
FB
EA
CS
Rev. 1.1 September 2010
is the desired crossover frequency. For best performance,
is set to be about 1/10 of the switching frequency;
C
C
total_loss
is 0.8V,
is the error amplifier transconductance, which is 200 x 10
is the current sense circuit transconductance, which is 6.68
=
=
C
---------------------
---------------------------------- -
2π
O
R
×
×
3
=
1.5
R
R
p1
3
L
V
×
IN
but lower than 1/5 of selected
f
P1
×
I
2
IN
can is selected by:
–
V
O
C
×
and resistor R
I
O
IN
pin, to the LX
C
together
www.aosmd.com
-6
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
The actual junction temperature can be calculated with
power dissipation in the AOZ1037 and thermal
impedance from junction to ambient.
The maximum junction temperature of AOZ1037 is
150°C, which limits the maximum load current capability.
Please see the thermal de-rating curves for maximum
load current of the AOZ1037 under different ambient
temperature.
The thermal performance of the AOZ1037 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
The AOZ1037 is an exposed pad SO-8 package. Layout
tips are listed below for the best electric and thermal
performance.
1. The exposed pad LX pins are connected to internal
2. Do not use thermal relief connection to the V
3. Input capacitor should be connected as close as
4. A ground plane is suggested. If a ground plane is
5. Make the current trace from the LX pins to L to C
6. Pour copper plane on all unused board area and
P
T
inductor_loss
junction
PFET and NFET drains. Connect a large copper
plane to the LX pins to help thermal dissipation.
and the PGND pin. Pour a maximized copper area
to the PGND pin and the VIN pin to help thermal
dissipation.
possible to the V
the LX voltage over-shoot. This is especially impor-
tant for V
not used, separate PGND from AGND and connect
them only at one point to avoid the PGND pin noise
coupling to the AGND pin.
the PGND as short as possible.
connect it to stable DC nodes, like V
=
IN
(
P
>16V.
=
total_loss
I
O
IN
2
×
pin and the PGND pin to reduce
R
inductor
–
P
inductor_loss
×
1.1
IN
, GND or V
) Θ
AOZ1037
Page 11 of 14
×
JA
IN
O
OUT
to
.