NCV3030ADR2G ON Semiconductor, NCV3030ADR2G Datasheet - Page 10

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NCV3030ADR2G

Manufacturer Part Number
NCV3030ADR2G
Description
IC PWM CTLR BUCK SYNC 8SOIC
Manufacturer
ON Semiconductor
Series
-r
Datasheet

Specifications of NCV3030ADR2G

Pwm Type
Voltage Mode
Number Of Outputs
1
Frequency - Max
1.44MHz
Duty Cycle
84%
Voltage - Supply
4.7 V ~ 28 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
OOV and OUV
the feedback pin of the output power stage. Two
comparators are placed on the feedback node of the OTA to
monitor the operating window of the feedback voltage as
shown in Figures 21 and 22. All comparator outputs are
ignored during the soft−start sequence as soft−start is
regulated by the OTA and false trips would be generated.
After the soft−start period has ended, if the feedback is
below the reference voltage of comparator 2 (V
The output voltage of the buck converter is monitored at
FB
Vref = 0.8 V
Hysteresis = 5 mV
Hysteresis = 5 mV
Figure 22. OOV and OUV Window Diagram
Figure 21. OOV and OUV Circuit Diagram
Vref*125%
Vref*75%
FB
< 0.8 V),
OOVP & Power Good = 0
OUVP & Power Good = 0
http://onsemi.com
Power Good = 1
Power Good = 1
10
the output is considered “undervoltage” and the device will
initiate a restart. When the feedback pin voltage rises
between the reference voltages of comparator 1 and
comparator 2 (0.8 < V
considered “Power Good.” Finally, if the feedback voltage
is greater than comparator 1 (V
voltage is considered “overvoltage,” and the device will
latch off. To clear a latch fault, input voltage must be
recycled. Graphical representation of the OOV and OUV is
shown in Figures 23 and 24.
Comparator 1
Comparator 2
Soft Start Complete
LOGIC
Voov = Vref * 125%
Vref = 0.8 V
Power Not Good Low
Vouv = Vref * 75%
Power Not good High
FB
< 1.0), then the output voltage is
FB
Latch off
Restart
> 1.0 V), the output

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