MT46H8M32LFB5-6:H Micron Technology Inc, MT46H8M32LFB5-6:H Datasheet - Page 66

• Manufacturer Part Number: MT46H8M32LFB5-6:H
• Description: IC SDRAM 256MB 166MHZ 90VFBGA
• Manufacturer: Micron Technology Inc
• Series: -r
• Type: DDR SDRAMr

Specifications of MT46H8M32LFB5-6:H

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Organization: 8Mx32
• Density: 256Mb
• Address Bus: 14b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 120mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 29: Data Output Timing –
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
DQ[15:8] and UDQS, collectively
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
DQ[7:0] and LDQS, collectively
DQ (Last data valid)
DQ (Last data valid)
DQ (Last data valid)
DQ (Last data valid)
Notes:
UDQS
LDQS
1.
2.
3. DQ transitioning after DQS transitions define the
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
5.
CK#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK
3
3
4
4
4
4
4
4
4
7
7
7
7
7
7
7
7
t
t
with DQS transition and ends with the last valid DQ transition.
er byte and UDQS defines the upper byte.
t
4
HP is the lesser of
DQSQ is derived at each DQS clock edge and is not cumulative over time and begins
QH is derived from
4
4
7
7
6
6
T1
t
DQSQ,
t HP
1
t
QH, and Data Valid Window (x16)
t HP
t
CL or
1
t DQSQ
t
HP:
t QH
t DQSQ
T2
5
t QH
Data valid
t
2
t
QH =
window
CH clock transition collectively when a bank is active.
66
Data valid
5
T2
T2
T2
window
t HP
2
T2
T2
T2
1
t
256Mb: x16, x32 Mobile LPDDR SDRAM
HP -
t DQSQ
T2n
t QH
t DQSQ
Data valid
t QH
5
t
window
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
QHS.
t HP
T2n
T2n
Data valid
T2n
5
window
2
1
T2n
T2n
T2n
T3
t DQSQ
t QH
t DQSQ
t QH
5
t HP
Data valid
2
window
Data valid
1
5
t
window
DQSQ window. LDQS defines the low-
T3
T3
T3
2
T3
T3n
T3
T3
t DQSQ
t DQSQ
t HP
t QH
t QH
1
Data valid
5
5
window
Data valid
©2008 Micron Technology, Inc. All rights reserved.
2
2
window
T3n
T3n
T4
T3n
T3n
T3n
T3n
READ Operation