DP83816AVNG/NOPB National Semiconductor, DP83816AVNG/NOPB Datasheet - Page 88

• Manufacturer Part Number: DP83816AVNG/NOPB
• Description: IC MEDIA ACCESS CTRLR 144-LQFP
• Manufacturer: National Semiconductor

Specifications of DP83816AVNG/NOPB

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 144-LQFP
• Mounting Type: Surface Mount
• For Use With: DP83816-MAAP - BOARD EVALUATION DP83816
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83816AVNG; *DP83816AVNG/NOPB; DP83816AVNG

6.0 Power Management and Wake-On-LAN
6.4.1 D0 State
The D0 state is the normal operational state of the device.
The PME Enable bit should be set to 0 to prevent packet
filtering based on the settings in the Wake Control/Status
Register (WCSR). It is also advisable to turn off all WOL
conditions in WCSR to prevent unnecessary PME
interrupts.
6.4.2 D1 State
The D1 state is the least power-saving Power Management
state, and might not be used by the operating system. The
device will only respond to PCI configuration transactions
and therefore will not transmit data. The only bus activity
the device can initiate is the assertion of the PMEN pin
(assuming the PME Enable bit is set to 1); no DMA activity
or interrupts will occur. The device will continue to receive
packets up to the limit of the receive FIFO size. Upon
returning to the D0 state, the system must re-enable I/O
and memory space in the device and turn on bus master
capability.
6.4.3 D2 State
The D2 state has the same features as the D1 state, and
the system may turn off the PCI clock, further reducing
power. The device will continue to receive packets up to
the limit of the receive FIFO size. Like the D1 state, the D2
state might not be used by the operating system.
6.4.4 D3hot State
The D3hot state is often known as the Standby state. If the
PME Enable bit is 0, or WOL is unconfigured, the device
saves power by turning off the Physical Layer Cell (PHY).
The system may turn off the PCI clock. In order to receive
packets in the D3hot state, both WOL mode and PME
Enable must be turned on. Like the D2 and D1 states, the
device will respond to PCI configuration transactions as
long as the PCI clock is running.
When the device exits the D3hot state, all PCI
configuration registers except for the PME Enable and
PME Status bits are reset to their default values. This
means the operating system must reinitialize the device’s
PCI configuration registers with valid base addresses, etc.
If PME Enable or WOL mode were not turned on, the
device must be fully reinitialized.
6.4.5 D3cold State
The D3cold state is the highest power-saving state; it is
often known as the Hibernate state. The PCI bus is turned
off, as is the PCI clock. If the PME Enable bit or WOL is
turned off, the PHY is turned off. This allows the device to
consume the least amount of power. The device must be
fully reinitialized after exiting this mode.
6.5 Wake-On-LAN (WOL) Mode
Wake-On-LAN Mode is a system-level function that allows
a network device to alert the system that a wake event has
occurred. It works in conjunction with the PCI Power
Management states detailed in the previous section. The
DP83816 supports several wake events including, but not
limited to, Wake on PHY Interrupt (i.e. link change), Wake
on Magic Packet, and Wake on Pattern Match. The
supported wake events appear in the device’s Wake
Command/Status Register (WCSR).
88
6.5.1 Entering WOL Mode
The following steps are required to place the DP83816 into
WOL mode:
1.
2.
3.
4.
5.
6.
7.
8.
The following two examples show the corresponding
register settings for Wake on Magic Packet mode and
Wake on PHY Interrupt mode respectively:
Entering Wake on Magic Packet mode:
1.
2.
3.
4.
5.
6.
Entering Wake on PHY Interrupt mode:
1.
2.
3.
4.
5.
6.
7.
8.
(Continued)
Disable the receiver by writing a 1 to the Receiver Dis-
able bit 3 (RXD) in the Command Register (CR - offset
00h in operational registers).
Write 0 to the Receive Descriptor Pointer Register
(RXDP - offset 30h in operational registers) to reset
the receive pointer.
Enable the receiver (now in “silent receive” mode) by
writing a 1 to the Receiver Enable bit 2 in the Com-
mand Register (CR:RXE).
Configure the Receive Filter Control Register (RFCR)
to enable the receive filter (RFCR:RFEN - bit 31) and
accept the desired type of wakeup packets. Note that
the Receive Filter Enable bit must be set to 1 for Wake
on PHY Interrupt as well.
If Wake on PHY Interrupt is desired, additionally con-
figure registers MICR (offset C4h in operational regis-
ters) and MISR (offset C8h in operational registers).
Configure
(WCSR) with the desired type of wake events. An
ACPI-compatible operating system should notify the
driver of these events.
Write a 1 to PME Enable, and set the desired Power
State in PMCSR. These can be done in one operation,
or PME Enable can be written first. An ACPI-compati-
ble operating system should handle this step.
If the Power Management state is D3cold, the system
will assert PCI reset, stop the PCI clock, and remove
power from the PCI bus.
CR = 00000008h (disable the receiver)
RXDP = 00000000h (reset the receive pointer)
CR = 00000004h (enable the receiver)
RFCR = F0000000h (enables the receive filter and
allows Broadcast, Multicast and Unicast packets to be
received - a Magic Packet could be any of those.)
WCSR = 00000200h (sets the Wake on Magic
Packet bit)
PMCSR = 00008103h (clears the PME status bit 15,
sets the PME Enable bit 8 and sets the Power State
bits [1:0] to D3hot)
CR = 00000008h (disable the receiver)
RXDP = 00000000h (reset the receive pointer)
CR = 00000004h (enable the receiver)
RFCR = 80000000h (enables the receive filter)
MICR = 00000002h (sets the Interrupt Enable bit 1)
MISR = 00000000h (unmasks the change of link sta-
tus event)
WCSR = 00000001h (sets the Wake on PHY interrupt
bit)
PMCSR = 00008103h (clears the PME status bit 15,
sets the PME Enable bit 8 and sets the Power State
bits [1:0] to D3hot)
the
Wake
Command/Status
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Register