Z1601720ASG1868 Zilog, Z1601720ASG1868 Datasheet - Page 70
![no-image](/images/manufacturer_photos/0/7/729/zilog_sml.jpg)
Z1601720ASG1868
Manufacturer Part Number
Z1601720ASG1868
Description
IC PCMCIA INTERFACE 100-VQFP
Manufacturer
Zilog
Datasheets
1.Z1601720ASC1868.pdf
(138 pages)
2.Z1601720ASG1868.pdf
(134 pages)
3.Z1601720ASG1868.pdf
(138 pages)
Specifications of Z1601720ASG1868
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
100-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part Number
Manufacturer
Quantity
Price
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56
EEPROM Register
Address: SELECT 13h
Name: Window 1 Range Address LSB
Type: Write/Read
Table 33.
EEPROM Register
Address: SELECT 14h
Name: Window 2 Control Register
Type: Write/Read
Table 34.
PS012002-1201
Bit Placement
Bits 7-0
Bit Placement
Bit 0
Bit 1
Bit 2
Bit 3
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
Window 1 Range Address LSB: Address 13h
Window 2 Control Register: Address 14h
Bit Name
Bit Name
DIS_PAC2
EN_PAC2_MEM
EN_PAC2_16
READ_PROTECT
Description
LSB range Address for Port 1
Description
When this bit is set to 1, it disables Port 2 address control
and decoder.
When this bit is set to 1, Memory Mode decoder is
enabled. When it is cleared, the I/O Mode decoder is
enabled.
When this bit is set, data swapping is provided internal to
the chip during data reads from the low byte of the ATA
bus to the PCMCIA bus high byte, and from the high byte
of the PCMCIA bus to the low byte of the ATA bus during
data writes. When this bit is cleared, it is high byte to high
byte and low byte to low byte.
Allows two cards at the same address to be read from.
When this bit is set, it prevents the PCMCIA bus from
becoming active.
Programming Internal Registers
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