Z1601720ASG1868 Zilog, Z1601720ASG1868 Datasheet - Page 53
Z1601720ASG1868
Manufacturer Part Number
Z1601720ASG1868
Description
IC PCMCIA INTERFACE 100-VQFP
Manufacturer
Zilog
Datasheets
1.Z1601720ASC1868.pdf
(138 pages)
2.Z1601720ASG1868.pdf
(134 pages)
3.Z1601720ASG1868.pdf
(138 pages)
Specifications of Z1601720ASG1868
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
100-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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EEPROM Register
Address: SELECT 02h
Name: Interface Configuration Register 1
Type: Read/Write
Table 14.
Programming Internal Registers
Bit Placement
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Interface Configuration Register 1: Address 02h
Bit Name
PDIAG_SET
EN_PDIAG
PDASP_SET
EN_DASP
EN_OR_CS01
EN_SPKR
EN_DASP_INT
EN_DASP_EXT
Z86017/Z16017 PCMCIA Interface Solution
Description
When set to 1, this bit activates PDIAG on the PCMCIA
bus side. On Power-On Reset, this bit is set to 0.
When set to 1, this bit drives the PCMCIA pin on the
PCMCIA side. On Power-On Reset, this bit is set to 0
(Table 15). Also see Registers 04h, 07h.
When set to 1, this bit sets the DASP pin on the PCMCIA
side. On Power-On Reset, this bit is set to 0.
When set to 1, this bit drives the DASP pin on the
PCMCIA side. On Power-On Reset, this bit is set to 0
(Table 16).
When set to 1, this bit is active and ATA_HCS0 has the
same level as ATA_HCS1. On Power-On Reset, this bit is
set to 0 (Table 17). Also see Register 03h (Table 19).
When set to 1, this bit is active and connects
EXTP_AUDIO (inverted) to the PC_BVD2//SPKR//
DASP/DREQ pin. On Power-On Reset, this bit is set to 0
(Table 18).
When set to 1, DASP is generated internally. On Power-On
Reset, this bit is set to 0.
When set to 1, DASP is generated externally from the
AT_DASP pin on the local AT bus side. On Power-On
Reset, this bit is set to 0. Also see Register 01h (Table 13).
Reference Manual
RM001102-0901
39
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