Z1601720ASG1868 Zilog, Z1601720ASG1868 Datasheet - Page 50
Z1601720ASG1868
Manufacturer Part Number
Z1601720ASG1868
Description
IC PCMCIA INTERFACE 100-VQFP
Manufacturer
Zilog
Datasheets
1.Z1601720ASC1868.pdf
(138 pages)
2.Z1601720ASG1868.pdf
(134 pages)
3.Z1601720ASG1868.pdf
(138 pages)
Specifications of Z1601720ASG1868
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
100-LQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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36
1. The pulse width of the /PC.IREQ signal in pulse mode is dependent on the clock period of the master clock input (TPMCKIN). The pulse
RM001102-0901
NOTES:
Register 0
Bit 1
0
0
1
1
0
0
1
1
width of the /PC.IREQ signal is equal to 192 x TPMCKIN.
Z86017/Z16017 PCMCIA Interface Solution
Reference Manual
Table 12.
Register 0
Bit 9
0
1
0
1
0
1
0
1
Master Clock
Clock In
50 ns
50 ns
50 ns
50 ns
100 ns
100 ns
100 ns
100 ns
EEPROM
CLK
Timing
6.4 µs
3.2 µs
800 ns
200 ns
12.8 µs
6.4 µs
1.6 µs
400 ns
Programming Internal Registers
Interrupt
Pulse
204 µs
102 µs
25 µs
5.25 µs
404 µs
204 µs
50 µs
12.5 µs
1
Width
Comments
Recommended
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