PX1011BI-EL1/G,557 NXP Semiconductors, PX1011BI-EL1/G,557 Datasheet - Page 15

IC PCI-EXPRESS X1 PHY 81-LFBGA

PX1011BI-EL1/G,557

Manufacturer Part Number
PX1011BI-EL1/G,557
Description
IC PCI-EXPRESS X1 PHY 81-LFBGA
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PX1011BI-EL1/G,557

Package / Case
81-LFBGA
Applications
PCI Express MAX to PCI Express PHY
Interface
JTAG
Voltage - Supply
1.2 V
Mounting Type
Surface Mount
Product
PHY
Supply Voltage (max)
1.3 V, 2.7 V, 3.6 V
Supply Voltage (min)
1.15 V, 2.3 V, 3 V
Supply Current
0.028 A
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Maximum Power Dissipation
300 mW
Number Of Channels
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935282114557
PX1011BI-EL1/G
PX1011BI-EL1/G

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PX1011BI-EL1/G,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
PX1011B_4
Product data sheet
8.10 Error detection
The PHY is responsible for detecting receive errors of several types. These errors are
signaled to the MAC layer using the receiver status signals RXSTATUS.
Table 15.
Because of higher level error detection mechanisms (like CRC) built into the data link layer
of PCI Express, there is no need to specifically identify symbols with errors. However,
timing information about when the error occurred in the data stream is important. When a
receive error occurs, the appropriate error code is asserted for one clock cycle at the point
closest to where the error actually occurred.
There are four error conditions that can be encoded on the RXSTATUS signals. If more
than one error should happen to occur on a received byte, the errors are signaled with the
priority shown below.
Operating mode
Received data OK
One SKP added
One SKP removed
Receiver detected
8b/10b decode error
Elastic buffer overflow
Elastic buffer underflow
Receive disparity error
1. 8b/10b decode error
2. Elastic buffer overflow
3. Elastic buffer underflow
4. Disparity error
Fig 10. Clock correction - remove a SKP
RXSTATUS2,
RXSTATUS1,
RXSTATUS0
RXDATA[7:0]
RXVALID
RXCLK
Function table PXPIPE status interface signals
active
000b
Rev. 04 — 4 September 2009
COM
010b
000b
SKP
Output pin
RXSTATUS2 RXSTATUS1 RXSTATUS0
L
L
L
L
H
H
H
H
PCI Express stand-alone X1 PHY
active
L
L
H
H
L
L
H
H
PX1011B
© NXP B.V. 2009. All rights reserved.
L
H
L
H
L
H
L
H
002aac176
15 of 30

Related parts for PX1011BI-EL1/G,557