PCA9548APW,112 NXP Semiconductors, PCA9548APW,112 Datasheet - Page 16

• Manufacturer Part Number: PCA9548APW,112
• Description: IC I2C SWITCH 8CH 24-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9548APW,112

• Package / Case: 24-TSSOP
• Applications: Translating Switch
• Interface: I²C, SMBus
• Voltage - Supply: 2.3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: Multiplexer
• Number Of Bits: 8
• Number Of Lines (input / Output): 8.0 / 1.0
• Propagation Delay Time: 0.3 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8.0
• Number Of Output Lines: 1.0
• Power Dissipation: 400 mW
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3384-5; 935275816112; PCA9548APW

NXP Semiconductors
11. Dynamic characteristics
Table 8.
[1]
[2]
[3]
[4]
[5]
PCA9548A_3
Product data sheet
Symbol
t
f
t
t
t
t
t
t
t
t
t
t
C
t
t
t
RESET
t
t
t
PD
SCL
BUF
HD;STA
LOW
HIGH
SU;STA
SU;STO
HD;DAT
SU;DAT
r
f
SP
VD;DAT
VD;ACK
w(rst)L
rst
REC;STA
b
Pass gate propagation delay is calculated from the 20
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
bridge the undefined region of the falling edge of SCL.
C
Measurements taken with 1 k pull-up resistor and 50 pF load.
b
= total capacitance of one bus line in pF.
Parameter
propagation delay
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time for a repeated START
condition
set-up time for STOP condition
data hold time
data set-up time
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
capacitive load for each bus line
pulse width of spikes that must be
suppressed by the input filter
data valid time
data valid acknowledge time
LOW-level reset time
reset time
recovery time to START condition
Dynamic characteristics
Rev. 03 — 7 July 2009
Conditions
from SDA to SDx,
or SCL to SCx
HIGH-to-LOW
LOW-to-HIGH
SDA clear
typical R
on
and the 15 pF load capacitance.
[2]
[5]
[5]
Standard-mode
Min
250
500
4.7
4.0
4.7
4.0
4.7
4.0
0
0
4
0
-
[3]
-
-
-
-
-
-
-
I
2
8-channel I
C-bus
0.3
1000
Max
3.45
100
300
400
0.6
50
1
1
-
-
-
-
-
-
-
-
-
-
[1]
IH(min)
2
20 + 0.1C
20 + 0.1C
C-bus switch with reset
Fast-mode I
of the SCL signal) in order to
PCA9548A
Min
100
500
1.3
0.6
1.3
0.6
0.6
0.6
0
0
4
0
-
-
-
-
-
-
[3]
© NXP B.V. 2009. All rights reserved.
b
b
[4]
[4]
2
C-bus
0.3
Max
400
300
300
400
0.9
0.6
50
1
1
-
-
-
-
-
-
-
-
-
-
[1]
16 of 26
Unit
ns
kHz
ns
ns
ns
pF
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s