PCA9548APW,118 NXP Semiconductors, PCA9548APW,118 Datasheet - Page 7

• Manufacturer Part Number: PCA9548APW,118
• Description: IC I2C SWITCH 8CH 24TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9548APW,118

• Package / Case: 24-TSSOP
• Applications: Translating Switch
• Interface: I²C, SMBus
• Voltage - Supply: 2.3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: Multiplexer
• Number Of Lines (input / Output): 8.0 / 1.0
• Propagation Delay Time: 0.3 ns at 2.3 V to 5.5 V
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8.0
• Number Of Output Lines: 1.0
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935275816118; PCA9548APW-T; PCA9548APW-T

NXP Semiconductors
PCA9548A_3
Product data sheet
6.2.1 Control register definition
6.3 RESET input
6.4 Power-on reset
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the
control register. This register is written after the PCA9548A has been addressed. The
2 LSBs of the control byte are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a STOP condition has been
placed on the I
the channel is made active, so that no false conditions are generated at the time of
connection.
Table 4.
Remark: Multiple channels can be enabled at the same time. Example: B7 = 0, B6 = 1,
B5 = 0, B4 = 0, B3 = 1, B2 = 1, B1 = 0, B0 = 0, means that channels 7, 5, 4, 1 and 0 are
disabled and channels 6, 3, and 2 are enabled. Care should be taken not to exceed the
maximum bus capacitance. Default condition is all zeroes.
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of t
its register and I
must be connected to V
When power is applied to V
a reset condition until V
and the PCA9548A register and I
states (all zeroes) causing all the channels to be deselected. Thereafter, V
lowered below 0.2 V to reset the device.
B7
X
X
X
X
X
X
X
0
1
B6
X
X
X
X
X
X
0
1
X
Control register: Write—channel selection; Read—channel status
2
C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when
B5
X
X
X
X
X
0
1
X
X
2
C-bus state machine and will deselect all channels. The RESET input
B4
X
X
X
X
0
1
X
X
X
DD
DD
Rev. 03 — 7 July 2009
has reached V
through a pull-up resistor.
DD
, an internal Power-On Reset (POR) holds the PCA9548A in
B3
X
X
X
0
1
X
X
X
X
2
C-bus state machine are initialized to their default
B2
X
X
0
1
X
X
X
X
X
POR
. At this point, the reset condition is released
B1
X
0
1
X
X
X
X
X
X
8-channel I
B0
0
1
X
X
X
X
X
X
X
w(rst)L
Command
channel 0 disabled
channel 0 enabled
channel 1 disabled
channel 1 enabled
channel 2 disabled
channel 2 enabled
channel 3 disabled
channel 3 enabled
channel 4 disabled
channel 4 enabled
channel 5 disabled
channel 5 enabled
channel 6 disabled
channel 6 enabled
channel 7 disabled
channel 7 enabled
, the PCA9548A will reset
2
C-bus switch with reset
PCA9548A
© NXP B.V. 2009. All rights reserved.
DD
must be
7 of 26