PCA9703PW,118 NXP Semiconductors, PCA9703PW,118 Datasheet - Page 16

• Manufacturer Part Number: PCA9703PW,118
• Description: IC SHIFT REG SPI GPI 24TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9703PW,118

• Package / Case: 24-TSSOP
• Applications: Automotive
• Interface: SPI Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Logic Family: PCA
• Operating Supply Voltage: 4.5 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Input Voltage: 5 V
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Frequency: 5 MHz
• Mounting Style: SMD/SMT
• Output Current: 6 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5114-2; PCA9703PW,118

NXP Semiconductors
11. Dynamic characteristics
Table 6.
V
PCA9703_1
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
max
r
f
WH
WL
SPILEAD
SPILAG
su(SDIN)
h(SDIN)
en(SDOUT)
dis(SDOUT)
v(SDOUT)
su(SCLK)
h(SCLK)
POR
rel(int)
v(INT)
DD
Fig 13. Timing diagram
= 4.5 V to 5.5 V; V
SDOUT
SCLK
SDIN
INT
CS
Dynamic characteristics
Parameter
maximum input clock frequency
rise time
fall time
pulse width HIGH
pulse width LOW
SPI enable lead time
SPI enable lag time
SDIN set-up time
SDIN hold time
SDOUT enable time
SDOUT disable time
SDOUT valid time
SCLK set-up time
SCLK hold time
power-on reset pulse time
interrupt release time
valid time on pin INT
high-impedance
t
su(SCLK)
SS
= 0 V; T
t
en(SDOUT)
t
SPILEAD
t
rel(int)
amb
t
=
su(SDIN)
50 %
−
40
°
MSB out
C to +125
MSB in
t
SCLK
SCLK
SDIN to SCLK falling edge
from rising edge of CS to SDOUT
from rising edge of SCLK;
SCLK rising after CS rising
Conditions
SDOUT; 10 % to 90 % at 5 V
SDOUT; 90 % to 10 % at 5 V
CS falling edge to SCLK rising edge
SCLK falling edge to CS rising edge
from SCLK falling edge
from CS LOW to
SDOUT low-impedance;
high-impedance;
SCLK falling to CS falling
time before CS is active
after V
after CS going LOW;
after INn changes or INT_EN
goes HIGH
h(SDIN)
Rev. 01 — 23 February 2010
DD
°
C; unless otherwise specified.
t
WH
> V
POR
t
v(SDOUT)
t
WL
Figure 16
18 V tolerant SPI 16-bit GPI with maskable INT
Figure 18
Figure 16
Figure 17
50 %
20
Min
-
-
-
50
50
50
50
30
-
-
-
50
50
-
-
-
t
dis(SDOUT)
t
SPILAG
Typ
-
35
25
-
-
-
-
-
-
-
-
-
-
-
-
-
200
PCA9703
t
© NXP B.V. 2010. All rights reserved.
h(SCLK)
002aac428
-
Max
5
60
50
-
-
-
-
-
55
85
55
-
-
250
500
800
16 of 27
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns