LTC4306IUFD Linear Technology, LTC4306IUFD Datasheet
LTC4306IUFD
Specifications of LTC4306IUFD
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LTC4306IUFD Summary of contents
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... Three address pins provide 27 distinct addresses. The LTC4306 is available in 24-lead QFN (4mm × 5mm) and SSOP packages. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patent pending. 10k 10k ...
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... LTC4306I ............................................. –40°C to 85°C Storage Temperature Range SSOP ................................................. –65°C to 150°C QFN ................................................... –65°C to 125°C Lead Temperature (Soldering, 10 sec) SSOP ................................................................ 300° ORDER PART NUMBER SCL3 SDA3 LTC4306CUFD ALERT LTC4306IUFD SDAIN GND SCLIN ENABLE PART MARKING* ALERT4 GPI01 4306 GPI02 ADR0 T ...
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ELECTRICAL CHARACTERISTICS range, otherwise specifications are SYMBOL PARAMETER V UVLO Threshold Hysteresis Voltage UVLOHYST V ENABLE Falling Threshold Voltage ENABLE Threshold Hysteresis Voltage ENHYST t ENABLE Delay, On-Off PHLEN t ENABLE Delay, Off-On PLHEN ...
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LTC4306 ELECTRICAL CHARACTERISTICS range, otherwise specifications are at T SYMBOL PARAMETER V ALERT1-ALERT4 Pin Input Falling ALERT1-4(IN) Threshold Voltages V ALERT1-ALERT4 Pin Input Threshold ALERT1-4(HY) Hysteresis Voltages Interface V ADR0-2 Input High Voltage ADR(H) V ADR0-2 Input ...
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W U TYPICAL PERFOR A CE CHARACTERISTICS Buffer Circuitry t PHL vs Temperature 120 100 100 125 –50 – TEMPERATURE (°C) 4306 G01 ...
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LTC4306 CTIO S (GN24 Package/UFD24 Package) ALERT (Pin 3/Pin 1): Fault Alert Output. An open-drain output that is pulled low when a fault occurs to alert the host controller. The LTC4306 pulls ALERT low when ...
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W BLOCK DIAGRA LTC4306 4306f 7 ...
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LTC4306 U OPERATIO Control Register Bit Definitions Register 0 (00h) BIT NAME TYPE* DESCRIPTION d7 Downstream R Indicates if upstream bus is connected Connected to any downstream buses 0 = upstream bus disconnected from all downstream buses 1 = upstream ...
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U OPERATIO Register 2 (02h) BIT NAME TYPE* DESCRIPTION d7 GPIO1 Mode R/W Configures Input/Output mode of Configure GPIO1 0 = output mode (default input mode d6 GPIO2 Mode R/W Configures Input/Output Mode of Configure GPIO2 0 = ...
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LTC4306 U OPERATIO The LTC4306 is a 4-channel, 2-wire bus multiplexer/ switch with bus buffers to provide capacitive isolation between the upstream bus and downstream buses. Mas- ters on the upstream 2-wire bus (SDAIN and SCLIN) can command the LTC4306 ...
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U OPERATIO V CC SDA1 N1 V SDA2 N2 Figure 1. Example of Unacceptable Level Shifting Rise Time Accelerators The Upstream Accelerators Enable and Downstream Ac- celerators Enable bits of register 1 activate the upstream and downstream rise time accelerators, ...
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LTC4306 U OPERATIO In all other cases, the LTC4306 communicates with the master to resolve the fault. After the master broadcasts the Alert Response Address (ARA), the LTC4306 will respond with its address on the SDAIN line and release the ...
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U OPERATIO 2 Table 1. LTC4306 I C Device Addressing HEX DEVICE DESCRIPTION ADDRESS h a6 Mass Write BA 1 Alert Response ...
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LTC4306 U OPERATIO a6-a0 SDA SCL 1-7 S START ADDRESS CONDITION a4-a0 START SLAVE ADDRESS a4-a0 WR ACK START SLAVE S ADDRESS 35Ω, making the GPIO pull-downs capable of ...
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U OPERATIO Fall Time Control 2 Per the I C Fast Mode (400kHz) Specification, the two- wire bus digital interface circuitry provides fall time con- trol when forcing logic lows onto the SDAIN bus. The fall time always meets the ...
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LTC4306 U U APPLICATIO S I FOR ATIO Assume in Figure 5 that the total parasitic bus capacitance on SDA1 due to trace and device capacitance is 100pF. To ensure that the boost currents are active during rising edges, the ...
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U U APPLICATIO S I FOR ATIO R2 R3 10k 10k µ 0.01µF 10k 10k SCL1 4 17 SCLIN SDA1 18 ALERT1 2 SDAIN 5 ENABLE 1 ...
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LTC4306 U U APPLICATIO S I FOR ATIO 10k 10k µ 10k V CC OPEN BACKPLANE CONNECTOR SCL1 4 SCLIN SDA1 ALERT1 2 SDAIN 5 ...
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... DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U UFD Package ...
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... Hot Swappable 2-Wire Bus Buffer with Low Voltage Level Translation LTC4303/LTC4304 How Swappable Bus Buffers with Stuck Bus Recovery LTC4305 2-Channel 2-Wire Multiplexer with Capacitance Buffering ThinSOT is a trademark of Linear Technology Corporation. Linear Technology Corporation 20 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 ● ...