LTC4306CUFD#TR Linear Technology, LTC4306CUFD#TR Datasheet - Page 9

• Manufacturer Part Number: LTC4306CUFD#TR
• Description: IC MUX 4CH 2-WIRE BUS 24-QFN
• Manufacturer: Linear Technology

Specifications of LTC4306CUFD#TR

• Applications: Multiplexer with Amplifier
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 2.2 V ~ 5.5 V
• Package / Case: 24-QFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

OPERATIO
Register 2 (02h)
BIT NAME
* For Type, “R/W” = Read Write, “R” = Read Only
**Stuck bus program table
d7 GPIO1 Mode
d6 GPIO2 Mode
d5 Connection
d4 GPIO1 Output
d3 GPIO2 Output
d2 Mass Write Enable
d1 Timeout Mode Bit 1 R/W Stuck Low Timeout Set Bit 1**
d0 Timeout Mode Bit 0 R/W Stuck Low Timeout Set Bit 0**
TIMSET1
Configure
Configure
Requirement
Mode Configure
Mode Configure
0
0
1
1
TIMSET0
U
0
1
0
1
TYPE* DESCRIPTION
R/W Configures Input/Output mode of
R/W Configures Input/Output Mode of
R/W Sets logic requirements for
R/W Configures GPIO1 Output Mode
R/W Configures GPIO2 Output Mode
R/W Enable Mass Write Address using
GPIO1
0 = output mode (default)
1 = input mode
GPIO2
0 = output mode (default)
1 = input mode
downstream buses to be connected
to upstream bus
0 = Bus Logic State bits (see register
3) of buses to be connected must be
high for connection to occur (default)
1 = Connect regardless of
downstream logic state
0 = open-drain pull-down (default)
1 = push-pull
0 = open-drain pull-down (default)
1 = push-pull
address (1011 101)b
0 = Disable Mass Write
1 = Enable Mass Write (default)
Timeout Disabled (Default)
Timeout After 7.5ms
Timeout After 30ms
Timeout After 15ms
TIMEOUT MODE
Register 3 (03h)
BIT NAME
* For Type, “R/W” = Read Write, “R” = Read Only
†
the master, so that the master can choose not to connect to a low
downstream bus. A given bit is a “don’t care” if its associated
downstream bus is already connected to the upstream bus.
d7 Bus 1 FET State
d6 Bus 2 FET State
d5 Bus 3 FET State
d4 Bus 4 FET State
d3 Bus 1 Logic State
d2 Bus 2 Logic State
d1 Bus 3 Logic State
d0 Bus 4 Logic State
These bits give the logic state of disconnected downstream buses to
TYPE* DESCRIPTION
R/W Sets and indicates state of FET
R/W Sets and indicates state of FET
R/W Sets and indicates state of FET
R/W Sets and indicates state of FET
R
R
R
R
switches connected to downstream
bus 1
0 = switch open (default)
1 = switch closed
switches connected to downstream
bus 2
0 = switch open (default)
1 = switch closed
switches connected to downstream
bus 3
0 = switch open (default)
1 = switch closed
switches connected to downstream
bus 4
0 = switch open (default)
1 = switch closed
Indicates logic state of downstream
bus 1; only valid when disconnected
from upstream bus
0 = SDA1, SCL1 or both are below 1V
1 = SDA1 and SCL1 are both above
1V
Indicates logic state of downstream
bus 2; only valid when disconnected
from upstream bus
0 = SDA2, SCL2 or both are below 1V
1 = SDA2 and SCL2 are both above
1V
Indicates logic state of downstream
bus 3; only valid when disconnected
from upstream bus
0 = SDA3, SCL3 or both are below 1V
1 = SDA3 and SCL3 are both above
1V
Indicates logic state of downstream
bus 4; only valid when disconnected
from upstream bus
0 = SDA4, SCL4 or both are below 1V
1 = SDA4 and SCL4 are both above
1V
LTC4306
†
†
†
†
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