LTC4306CUFD#TR Linear Technology, LTC4306CUFD#TR Datasheet - Page 14

• Manufacturer Part Number: LTC4306CUFD#TR
• Description: IC MUX 4CH 2-WIRE BUS 24-QFN
• Manufacturer: Linear Technology

Specifications of LTC4306CUFD#TR

• Applications: Multiplexer with Amplifier
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 2.2 V ~ 5.5 V
• Package / Case: 24-QFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

OPERATIO
LTC4306
14
is 35Ω, making the GPIO pull-downs capable of driving
LEDs. At V
and the typical pull-down impedance is 20Ω. In open-
drain output mode, the user provides the logic high by
connecting a pull-up resistor between the GPIO pin and an
external supply voltage. The external supply voltage can
range from 1.5V to 5.5V independent of the V
In input mode, the GPIO input threshold voltage is 1V.
The GPIO1 and GPIO2 Logic State bits in register 1
indicate the logic state of the two GPIO pins. The logic-
level threshold voltage for each pin is 1V. The GPIO1 and
GPIO2 Output Driver State bits in register 1 indicate the
logic state that the LTC4306 is attempting to write to the
GPIO pins. This is useful when the GPIOs are being used
SDA
SCL
CC
START
1
= 5V, the typical pull-up impedance is 320Ω
CONDITION
START
U
ADDRESS
S
10 a4-a0
SLAVE
7
START
ADDRESS
1
a6-a0
WR
1-7
1
0
ADDRESS
10 a4-a0
SLAVE
ACK
7
1
S
0
S
1
R/W
8
XXXXXX r1r0
Figure 3. Data Transfer Over I
REGISTER
0001 100
Figure 4. Protocols Accepted by LTC4306
WR
1
0
8
7
ACK
9
CC
ALERT RESPONSE ADDRESS PROTOCOL
ACK
1
S
0
voltage.
RD
1
1
WRITE BYTE PROTOCOL
ACK
READ BYTE PROTOCOL
1
S
0
1-7
XXXXXX r1r0
REGISTER
d7-d0
DATA
ACK
START
8
1
S
0
1
in open-drain output mode and one or more external
devices are connected to the GPIOs. If the LTC4306 is
trying to write a high to a GPIO pin, but the pin’s actual
logic state is low, then the LTC4306 knows that the low is
being forced by an external device.
Glitch Filters
The LTC4306 provides glitch filters on the SDAIN and
SCLIN pins as required by the I
Specification. The filters prevent signals of up to 50ns
(minimum) time duration and rail-to-rail voltage
magnitude from passing into the two-wire bus digital
interface circuitry.
DEVICE ADDRESS
8
ADDRESS
10 a4-a0
SLAVE
ACK
2
1
S
0
7
8
C or SMBus
ACK
9
RD
d7-d0
DATA
1
1
BYTE
ACK
M
8
1
1
1-7
ACK
1
S
0
P
4306 F04
d7-d0
DATA
1
ACK
1
S
0
8
d7-d0
DATA
BYTE
8
STOP
1
2
ACK
C Fast Mode (400kHz)
9
ACK
M
1
1
CONDITION
STOP
STOP
P
1
4306 F03
4306f