IXDP610PI IXYS, IXDP610PI Datasheet
IXDP610PI
Specifications of IXDP610PI
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IXDP610PI Summary of contents
Page 1
... Outputs may be disabled under G software control Special locking bit prevents damage G to the stage in the event of a software failure 18-pin slim DIP package G Dimensions in inch and mm 18-Pin Slim DIP °C © 2001 IXYS/DEI All rights reserved ...
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... When Writing Stop to the Control latch 13 t RST Low Time RLRH * Output will change 1 rising CLOCK edge +5ns after WR (see Fig 1/f clk clk © 2001 IXYS/DEI All rights reserved Maximum Ratings min. max. 4.5 5.5 -40 85 Characteristic Values min. typ. ...
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... Pin Description IXDP 610PI IXYS IXDP610PI Sym. Pin Description DATA BUS - the data bus the IXDP610 is configured for D2 3 input only. Data to be written the IXDP610 is placed on data D4 5 lines D0 through D7 during microprocessor write cycle Data is accepted by the D7 8 IXDP610 when CHIP SELECT ...
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... Pulse Width latch whenever a change in duty cycle is desired. This is analo- SEPI Fig. 1 Basic System Configuration © 2001 IXYS/DEI All rights reserved gous to writing data to a DAC. Programmable dead-time Because the IXDP610 is a digital IC, and is programmable possible to ...
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... PWM outputs. Percent duty cycle is defined as follows: (assuming zero dead-time) For OUT1: time duty cycle = x 100 PWM cycle time For OUT2: time duty cycle = x 100 PWM cycle time “PWM cycle time” Fig. 2. CYCLE © 2001 IXYS/DEI All rights reserved ). ...
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... Table 3: Duty Cycle as a Function of PW Number Fig. 4 8051 to IXDP610 Interface © 2001 IXYS/DEI All rights reserved extremes. The following table illustrates the resulting percent duty cycle for seve-ral PW numbers. (The complete table would have 256 entries, those entries that have been omitted can be calcu-lated using the above formulare ...
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... MHz bit bit 10.9 0.363 38 10.9 0.547 25 5.5 0.547 25 10.9 1.094 12 2.7 0.547 25 5.5 1.094 12 5.5 1.094 12 10.9 2.188 6 2.7 1.367 10. 5.5 2.734 5. 5.5 2.734 5. 10.9 5.469 2. 2.7 5.469 2. 5.5 10.94 1. 5.5 10.94 1. 10.9 21.88 0. © 2001 IXYS/DEI All rights reserved ...
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... Fig. 6b and Fig. 7 Effect of Changing the Duty Cycle during a PWM Cycle © 2001 IXYS/DEI All rights reserved have only one dead-time period in- serted in each PWM cycle. In Fig. 6b the desired ontime of OUT1 is less than the one dead-time period, there- fore OUT1 can never turn on ...