PTN3392BS,518 NXP Semiconductors, PTN3392BS,518 Datasheet
PTN3392BS,518
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PTN3392BS,518 Summary of contents
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PTN3392 2-lane DisplayPort to VGA adapter IC Rev. 2 — 15 July 2010 1. General description The PTN3392 is a DisplayPort to VGA adapter IC designed to connect a DisplayPort source to a VGA sink. The PTN3392 integrates a DisplayPort ...
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... NXP Semiconductors 2.3 Analog video output VSIS 1.2 compliance Analog RGB current-source outputs VSYNC and HSYNC outputs Pixel clock up to 240 MHz Triple 8-bit Digital-to-Analog Converter (DAC) Direct drive of double terminated 75 Ω load with standard 700 mV (peak-to-peak) signals 2.4 General features Supports ‘ ...
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... NXP Semiconductors 3. Applications Dongle PC accessory Dongle connected to PC DisplayPort output and connected to RGB monitor via VGA cable PTN3392 is powered by the DP_PWR pin on the DisplayPort connector Desktop and notebook computers Notebook docking stations 4. Ordering information Table 1. Ordering information Type number Topside mark ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 2. Symbol VDDD VDDA VDDA_DP VDD_IO VDD_DAC GND_IO GND_DAC GNDA_DP0 GNDA_DP1 [1] GNDA [1] GNDD PTN3392 Product data sheet terminal 1 index area RESET_N 1 CLK_O 2 3 HPD 4 VDDA_DP TCK 5 TDO 6 PTN3392BS GND_IO 7 8 TMS ...
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... NXP Semiconductors Table 2. Symbol DisplayPort ML0_P ML0_N ML1_P ML1_N AUX_P AUX_N HPD RGB DAC outputs BLU BLU_N GRN GRN_N RED RED_N RSET DDC SCL SDA Monitor-side sync HSYNC VSYNC JTAG TCK TDO TMS TRST_N TDI PTN3392 Product data sheet Pin description … ...
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... NXP Semiconductors Table 2. Symbol Strap pins, S[3: Miscellaneous RESET_N CLK_O LDOCAP_CORE 30 OSC_IN OSC_OUT LDOCAP_AUX RRX [1] HVQFN48 package die supply ground is connected to both GND pins and exposed center pad. GND pins 7, 23, 28, 29, 41, 45, 48, and exposed center pad must be connected to supply ground for proper device operation ...
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... NXP Semiconductors 7. Functional description Referring to AC-coupled high speed differential signaling protocol into a VESA VSIS 1.2 compliant analog VGA signaling. The PTN3392 integrates a DisplayPort receiver (according to VESA DisplayPort v1.1a specification, digital-to-analog converter that supports display resolution from VGA to WUXGA (see Table 4 “Display resolution and pixel clock PTN3392 supports one or two DisplayPort v1 ...
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... NXP Semiconductors 7.3 DPCD registers DPCD registers that are part of the VESA DisplayPort v1.1a are described in detail in Ref. 1. The following paragraphs only describe the specific implementation by PTN3392. The PTN3392 DisplayPort receiver capability and status information about the link are reported by DisplayPort Configuration Data (DPCD) registers, when a DisplayPort source issues a read command on the AUX CH ...
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... NXP Semiconductors Table 3. DPCD register Automated testing sub-field (optional) 00218h to 0027Fh Branch device specific field 00500h 00501h 00502h 00503h 00504h 00505h 00506h 00507h 00508h 00509h 0050Ah, 0050Bh 0050Ch to 005FFh [1] Byte fields that are not explicitly listed are by definition reserved (‘RES’) and their default value is 0h. ...
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... NXP Semiconductors 2 7.3 over AUX CH registers 2 7.3.2.1 I C-bus speed control register (read only, 0000Ch) Bit or bits are set to indicate I DisplayPort source reads register 0000Ch and sets the I DPCD register 00109h setting. The PTN3392 then adapts its I set by the DisplayPort source. 2 7.3.2.2 I ...
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... NXP Semiconductors The PTN3392 implements two different ways to handle the HPD signal. The HPD behavior is governed by the S0 pin’s value after the reset and initialization sequence is completed (see • tied LOW, HPD is driven HIGH irrespective of whether a VGA monitor is detected. • pin is tied HIGH, HPD is only driven HIGH when a monitor is detected. ...
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... NXP Semiconductors 7.4 logic left open-circuit (internal pull-down) (DisplayPort v1.1a compliant behavior), PTN3392 behaves as stated in VESA DisplayPort v1.1a, sections 7 and 8. PTN3392 will keep HPD LOW during its internal initialization sequence after power-up. It will then update DPCD register SINK_COUNT to the expected value, depending if a VGA monitor is detected or not, and will then assert HPD HIGH whatever is the value of SINK_COUNT register ...
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... NXP Semiconductors 7.6 Triple 8-bit video DACs and VGA outputs The triple 8-bit video DACs output a 700 mV (peak-to-peak) analog video output signal into 37.5 Ω load the case of a doubly terminated 75 Ω cable. The DAC is capable of supporting the maximum pixel rate supported by a two-lane DP link (240 MHz). ...
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V V DD(3V3) DD(3V3)AUX 47 Ω at 100 MHz 2 1 0.1 μF 2.2 μ 0.1 μF J1 2.2 μF LANE0p 1 GND 2 LANE0n 12 kΩ 3 LANE1p 4 GND 5 LANE1n 6 LANE2p 7 GND 8 ...
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... NXP Semiconductors 9.1 Display resolution Table 4 (Refer to Table 4. Display resolution and pixel clock rate Display Active video type Horizontal Vertical VGA 640 480 SVGA 800 600 XGA 1024 768 SXGA 1280 1024 SXGA 1280 1024 UXGA 1600 1200 UXGA 1600 1200 ...
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... NXP Semiconductors 10. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V analog supply voltage DDA V digital supply voltage DDD V input voltage I T storage temperature stg V electrostatic discharge voltage ESD [1] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model - Component level; ...
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... NXP Semiconductors 12. Characteristics 12.1 Current consumption, power dissipation and thermal characteristics Table 7. Current consumption, power dissipation and thermal characteristics Symbol Parameter I supply current DD I standby supply current DD(stb) P power dissipation R thermal resistance from junction th(j-a) to ambient R pull-up resistance PU R pull-down resistance pd 12 ...
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... NXP Semiconductors [3] Informative; refer to Figure 7 for definition of differential voltage. [4] t specifies the total allowable Deterministic Jitter (DJ). RX_EYE_m-mJT_CHP 1 − t [5] specifies the allowable Total Jitter (TJ). RX_EYE_CONN [6] Common mode voltage is equal to V [7] Total drive current of the input bias circuit when it is shorted to its ground. ...
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... NXP Semiconductors = 2 × |V − V [6] V AUX_DIFFp-p AUX+ AUX− [7] Common-mode voltage is equal to V [8] Steady-state common-mode voltage shift between transmit and receive modes of operation. [9] Total drive current of the transmitter when it is shorted to its ground. [10] The AUX CH AC coupling capacitor placed both on the DisplayPort source and sink devices. ...
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... NXP Semiconductors 12.6 DAC Table 12. DAC characteristics Symbol Parameter N DAC resolution res(DAC) f clock frequency clk ΔI DAC output current variation o(DAC) INL integral non-linearity DNL differential non-linearity V DAC output voltage o(DAC) C DAC output capacitance o(DAC) α DAC crosstalk ct(DAC) 12.7 HSYNC, VSYNC characteristics Table 13 ...
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... NXP Semiconductors 12.9 JTAG and RESET_N Table 15. JTAG and RESET_N characteristics Symbol Parameter Input characteristics V HIGH-level input voltage IH V LOW-level input voltage IL Output characteristics V HIGH-level output voltage OH V LOW-level output voltage OL PTN3392 Product data sheet Conditions RESET_N JTAG −4 mA RESET_N −2 mA JTAG ...
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... NXP Semiconductors 13. Package outline HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 9. For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 18. Acronym AUX CH BER bpc CDM CMOS DAC DDC DJ DP DPCD ECC EDID ESD HBM HBR HDCP HPD 2 I C-bus IEC PTN3392 ...
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... NXP Semiconductors Table 18. Acronym I/O LSB MCCS MSB QXGA RBR RGB SSC SVGA SXGA TJ UI UXGA VESA VGA VSIS WUXGA XGA 16. References [1] VESA DisplayPort Standard — Version 1, Revision 1a; January 11, 2008 [2] Display Data Channel Command Interface Standard — Version 1.1; October 29, 2004 [3] Video Signal Standard (VSIS) — ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 VESA compliant DisplayPort v1.1a converter 2.2 DDC channel output . . . . . . . . . . . . . . . . . . . . . 1 2.3 Analog video output . . . . . . . . . . . . . . . . . . . . . 2 2.4 General features . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description ...