PCA9703PW,112 NXP Semiconductors, PCA9703PW,112 Datasheet - Page 7

• Manufacturer Part Number: PCA9703PW,112
• Description: IC SPI GPI 16-BIT 24TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9703PW,112

• Rohs Status: RoHS Compliant
• Applications: Automotive
• Interface: SPI Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 24-TSSOP
• Mounting Type: Surface Mount
• Other names: 568-5052-5

NXP Semiconductors
PCA9703_1
Product data sheet
Fig 4. Register access timing
interrupt mask
DATA[15:0] is data on the input pins, IN[15:0].
Shaded areas indicate active but invalid data.
input status
SDOUT
register
register
register
SCLK
SDIN
shift
7.1.6 Software reset operation
CS
7.2 Interrupt output
high-impedance
Software reset will be activated by writing all zeroes into the shift register. This is identical
to having an interrupt mask value of 0X00. Such an operation will reset the device, clear
the input status register to zero and set the interrupt output to HIGH (no interrupt).
INT is the open-drain interrupt output and is active LOW. A pull-up resistor of
approximately 10 kΩ is recommended.
A user-defined interrupt mask bit pattern is shifted into the shift register via SDIN. The
value of bits in the mask pattern will determine which input pins will cause an interrupt.
Any bit that is = 0 will disable the input pin corresponding to that bit position from
generating an interrupt. Interrupts will be enabled for bits having value = 1. The mask bit
pattern is not automatically aligned with the desired input pins. It is the responsibility of the
programmer to shift the correct number of (mask) bits to the correct positions into the shift
register. The interrupt mask bit pattern must be positioned into the shift register prior to the
CS rising edge. Misaligned mask pattern will result in unexpected activation of the
interrupt signal.
The interrupt output is asserted when the input status is changed, and the interrupt mask
bit corresponding to the input pin that caused the change is unmasked (bit value = 1), and
is cleared on the falling edge of CS or when the input port status matches the input status
register. When there are multiple devices, the INT outputs may be tied together to a single
pull-up.
DATA[15:0]
MSB out
Rev. 01 — 23 February 2010
sample
MSB in
SDIN
DATA[15:0]
MSB − 1 out
MSB − 1 in
18 V tolerant SPI 16-bit GPI with maskable INT
LSB out
LSB in
PCA9703
© NXP B.V. 2010. All rights reserved.
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