PCA9549PW,112 NXP Semiconductors, PCA9549PW,112 Datasheet - Page 8

• Manufacturer Part Number: PCA9549PW,112
• Description: IC 8-BIT BUS SW 24-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9549PW,112

• Package / Case: 24-TSSOP
• Applications: Translating Switch
• Interface: I²C, SMBus
• Voltage - Supply: 2.3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• On Resistance (max): 15 Ohms
• Propagation Delay Time: 0.25 ns
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Function: I2C Bus Switch
• High Level Output Current: - 25 mA
• Low Level Output Current: 25 mA
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Organization: 8 x 1:1
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Number Of Circuits: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3386-5; 935282231112; PCA9549PW

NXP Semiconductors
7. Characteristics of the I
PCA9549_2
Product data sheet
7.1.1 START and STOP conditions
7.1 Bit transfer
7.2 System configuration
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
Fig 8.
Fig 9.
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
Bit transfer
Definition of START and STOP conditions
START condition
2
SDA
SCL
Figure
C-bus
S
Rev. 02 — 13 July 2009
Octal bus switch with individually I
9).
Figure
data valid
data line
stable;
10).
Figure
allowed
change
of data
8).
2
C-bus controlled enables
STOP condition
mba607
PCA9549
P
© NXP B.V. 2009. All rights reserved.
mba608
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