DS90LV001TMX/NOPB National Semiconductor, DS90LV001TMX/NOPB Datasheet - Page 3

• Manufacturer Part Number: DS90LV001TMX/NOPB
• Description: IC BUFFER LVDS/LVDS 3.3V 8-SOIC
• Manufacturer: National Semiconductor
• Type: Bufferr

Specifications of DS90LV001TMX/NOPB

• Tx/rx Type: LVDS
• Delay Time: 2.0ns
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 70mA
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• For Use With: LVDS001EVK - BOARD EVALUATION DS90LV001
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Capacitance - Input: -
• Other names: DS90LV001TMX

t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
PHLD
PLHD
SKD1
SKD3
SKD4
LHT
HLT
PHZ
PLZ
PZH
PZL
DJ
RJ
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3)
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V
ΔV
Note 3: All typical are given for V
Note 4: Output short circuit current (I
Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT (process, voltage and
temperature) range.
Note 6: t
the same channel.
Note 7: t
applies to devices at the same V
Note 8: t
operating temperature and voltage ranges, and across process distribution. t
Note 9: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT range with the following
test equipment setup: HP8133A (pattern pulse generator), 5 feet of RG142B cable with DUT test board and HP83480A (digital scope mainframe) with HP83484A
(50GHz scope module). The HP8133A with RG142B cable exhibit a t
OD
.
SKD4
SKD1
SKD3
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Pulse Skew |t
Part to Part Skew (Notes 5, 7)
Part to Part Skew (Notes 5, 8)
Rise Time (Note 5)
Fall Time (Note 5)
Disable Time (Active High to Z)
Disable Time (Active Low to Z)
Enable Time (Z to Active High)
Enable Time (Z to Active Low)
LVDS Data Jitter, Deterministic (Peak-to-Peak)
(Note 9)
LVDS Clock Jitter, Random (Note 9)
, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices over recommended
, |t
, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
PLHD
− t
PHLD
PLHD
|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
− t
CC
CC
Parameter
and within 5°C of each other within the operating temperature range.
PHLD
= +3.3V and T
OS
) is specified as magnitude only, minus sign indicates direction only.
| (Notes 5, 6)
A
= +25°C, unless otherwise stated.
DJ
= 21ps and t
R
Figure 3 and Figure 4
R
Figure 3 and Figure 5
R
Figure 6 and Figure 7
V
= 1.2V at 800Mbps (NRZ)
V
clock
ID
ID
L
L
L
SKD4
= 100Ω, C
= 100Ω, C
= 100Ω, C
= 300mV; PRBS = 2
= 300mV; V
3
is defined as |Max − Min| differential propagation delay.
RJ
= 1.8ps.
L
L
L
Conditions
= 5pF
= 5pF
= 5pF
CM
= 1.2V at 400MHz
23
− 1 data; V
CM
Min
200
200
1.0
1.0
Typ
320
310
100
1.4
1.4
2.2
20
25
25
0
3
3
www.national.com
Max
200
400
450
450
135
2.0
2.0
3.5
60
25
25
45
45
OD
Units
and
ns
ns
ps
ps
ps
ps
ps
ns
ns
ns
ns
ps
ps