PCA9600DP/S911,118 NXP Semiconductors, PCA9600DP/S911,118 Datasheet - Page 16

• Manufacturer Part Number: PCA9600DP/S911,118
• Description: IC DUAL BI-DIR BUS BUFF 8-TSSOP
• Manufacturer: NXP Semiconductors
• Type: Bufferr

Specifications of PCA9600DP/S911,118

• Tx/rx Type: I²C Logic
• Delay Time: 100ns
• Capacitance - Input: 10pF
• Voltage - Supply: 2.5 V ~ 15 V
• Current - Supply: 7.3mA
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP
• For Use With: 568-4704 - DAUGHTER CARD PCA9600 FOR OM6275
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935285245118; PCA9600DP/S911-T; PCA9600DP/S911-T

NXP Semiconductors
PCA9600_4
Product data sheet
the master reaching the slave
rising edge
reaching the master
The master microcontroller should be programmed to produce a nominal SCL LOW
period as follows:
SCL LOW
The actual LOW period will become (the programmed value + the stretching time B).
When this actual LOW period is then less than the specified minimum, the specified
minimum should be used.
Example 1:
Example 2:
It is required to connect an Fm+ slave, with Rs
Fast-mode system also having 100 ns Rm
bus with 4 nF loading and 160
Calculate the allowed bus speed:
The maximum Fm+ slave response delay must be < 450 ns so the programmed LOW
period is calculated as:
The actual LOW period will be 887.5 + 285 = 1173 ns, which is below the Fast-mode
minimum, so the programmed LOW period must be increased to
(1300
shows that this Fast-mode system may be safely run to its limit of 400 kHz.
It is required to buffer a Master with Fm+ speed capability, but only 3 mA sink capability,
to an Fm+ bus. All the system operates at 3.3 V. The Master Rm
Only one PCA9600 is used. The Fm+ bus becomes the buffered bus. The Fm+ bus has
200 pF loading and 150
specified data valid time t
Calculate the allowed maximum system bus speed. (Note that the fixed values in the
delay equations represent the internal propagation delays of the PCA9600. Only one
PCA9600 is used here, so those fixed values used below are taken from the
characteristics.)
The delays are:
The programmed LOW period is calculated as:
Delay A = 120 + 85 + (2.5 + [4
Delay B = 115 + 100 + 70 = 285 ns
Delay C = 115 + 20 + 0.7(100 + 100) = 275 ns
LOW
Delay A = 40 + 56 + (2.5 + [4
Delay B = 115 + 50 + 21 = 186 ns
Delay C = 70 + 0.7(50 + 30) = 126 ns
SCL LOW
285) = 1015 ns, so the actual LOW equals the 1300 ns requirement and this
(Figure
450 + 347.5
slave response delay to valid data on its SDA
300 + 117
16) plus total delays in the slave's response data, carried on SDA,
(Figure
Rev. 04 — 11 November 2009
285 + 275 + 100 = 887.5 ns
VD;DAT
17).
pull-up, so its Rb
186 + 126 + 50 = 407 ns
(Figure
maximum of 300 ns.
pull-up.
0.2])
4])
15) minus the effective delay (stretch) of the SCL
5 + 50 = 347.5 ns
3.3 = 107 ns
Cm using two PCA9600’s to buffer a 5 V
Cb product is 30 ns. The Fm+ slave has a
Cs product of 100 ns, to a 5 V
+
A B
–
Dual bidirectional bus buffer
+
C
+
data set-up time
Cm product is 50 ns.
PCA9600
© NXP B.V. 2009. All rights reserved.
16 of 30
ns
(1)