PI2EQX5864CZFE Pericom Semiconductor, PI2EQX5864CZFE Datasheet - Page 3

• Manufacturer Part Number: PI2EQX5864CZFE
• Description: IC PCI-E REDRIVER 56TQFN
• Manufacturer: Pericom Semiconductor
• Series: ReDriver™r
• Type: Redriverr

Specifications of PI2EQX5864CZFE

• Tx/rx Type: CML
• Capacitance - Input: 50pF
• Voltage - Supply: 1.15 V ~ 1.25 V
• Current - Supply: 800mA
• Mounting Type: Surface Mount
• Package / Case: 56-TQFN
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Compliant

DESCRIPTION of OPERATION
Confi guration Modes
Device confi guration can be performed in two ways depending on the state of the MODE input. MODE determines whether IC
confi guration status is from the input pins or via I
tion operating state as stored in confi guration registers. While MODE is set high, changes to these control registers are disabled and
the initial condition is protected from any changes to insuring a known operating state. When the MODE pin is low, reprogramming
of these control registers via I
access.
During initial power-on, the value at the confi guration input pins: LB#, RESET#,RXD_A and RXD_B, will be latched to the con-
fi guration registers as initial startup states.
Equalizer Confi guration
The PI2EQX5864C input equalizer compensates for signal attenuation and Inter-Symbol Interference (ISI) resulting from long signal
traces or cables, vias, signal crosstalk and other factors, by boosting the gain of high-frequency signal components. Because either
too little, or too much, signal compensation may be non-optimal eight levels are provided to adjust for any application.
Equalizer confi guration can be programmed via I
equalization control, and all four channels within the group are assigned the same confi guration state. The Equalizer Selection table
below describes the register state and associated operation of the equalizer.
Equalizer Selection
Pin #
24
50
22
53
52
55, 56, Center Pad
1, 6, 11, 16, 21, 29,
34, 39, 44, 49
SEL2_[A:B]
0
0
0
0
1
1
1
1
09-0002
Pin Name
RESET#
RXD_A
RXD_B
SCL
SDA
GND
VDD
SEL1_[A:B]
0
0
1
1
0
0
1
1
2
C is allowed. Note that the MODE pin is not latched, and is always active to enable or disable I
Type
I
I
I
I/O
I/O
PWR
PWR
2
2
C when the mode pin is low. Each group of four channels, A and B, has separate
Description
RESET# is an active low channel reset input for Channel A0, B0, A1, B1, A2,
B2, A3 and B3 with internal 100K-Ohm pull-up resistor. When low, receiver
detection cycle is reset, and normal detection cycle is carry on after the pin goes
high.
Receiver detect enable input for Channel A0, A1, A2 and A3 with internal 100K-
Ohm pull-up resistor.
Receiver detect enable input for Channel B0, B1, B2 and B3 with internal 100K-
Ohm pull-up resistor.
I
I
Supply Ground
1.2V Supply Voltage
C control. When MODE is set high, the confi guration input pins set the confi gura-
2
2
C SCL clock input.
C SDA data input.
SEL0_[A:B]
0
1
0
1
0
1
0
1
3
with Equalization, Emphasis and I
@1.25GHz
0.5dB
0.6dB
1.0dB
1.9dB
2.8dB
3.6dB
5.0dB
7.7dB
5.0Gbps 4-Lane PCIe
@2.5GHz
1.2dB
1.5dB
2.6dB
4.3dB
5.8dB
7.1dB
9.0dB
12.3dB
®
2.0 ReDdriver™
PS8934D
PI2EQX5864C
2
C Control
2
07/08/09
C