PI2EQX5864CZFE Pericom Semiconductor, PI2EQX5864CZFE Datasheet - Page 16
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PI2EQX5864CZFE
Manufacturer Part Number
PI2EQX5864CZFE
Description
IC PCI-E REDRIVER 56TQFN
Manufacturer
Pericom Semiconductor
Series
ReDriver™r
Type
Redriverr
Datasheet
1.PI2EQX5864CZFE.pdf
(20 pages)
Specifications of PI2EQX5864CZFE
Tx/rx Type
CML
Capacitance - Input
50pF
Voltage - Supply
1.15 V ~ 1.25 V
Current - Supply
800mA
Mounting Type
Surface Mount
Package / Case
56-TQFN
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Delay Time
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PI2EQX5864CZFE
Manufacturer:
Pericom
Quantity:
135
Company:
Part Number:
PI2EQX5864CZFE
Manufacturer:
Pericom
Quantity:
367
SDA and SCL I/O for I
Characteristics of the SDA and SCL bus lines for F/S-mode I
Notes:
1. All values referred to V
2. A device must initially provide a hold time of at least 300 ns for the SDA signal (referred to the V
region of the falling edge of SCL.
Symbol
V
V
V
V
Symbol
t
t
t
t
t
HD;DAT
IH
IL
OL
hys
HD;STA
SU;DAT
SU;STO
SU;STA
t
t
f
t
HIGH
LOW
BUF
SCL
C
t
t
r
f
b
09-0002
SCL clock frequency
Hold time (repeated) START condition.
After this period, the fi rst clock pulse is
generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condi-
tion
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Buss free time between a STOP and
STOP condition
Capacitive load for each bus line
Parameters
DC input logic high
DC input logic low
DC output logic low
Hysteresis of Schmitt trigger input
IHmin
2
C-bus (V
and V
Parameter
ILmax
DD
levels.
= 1.2 ± 0.05v, T
A
Conditions
= 0 to 70°C)
Conditions
I
OL
16
= 3mA
2
C-bus devices
with Equalization, Emphasis and I
1.1
-0.3
0.2
Min.
Min.
5.0Gbps 4-Lane PCIe
250
4.0
4.7
4.0
4.7
5.0
4.0
4.7
0
–
–
(1)
IHmin
of the SCL signal) to bridge the undefi ned
Typ.
Typ.
V
DD
Max.
Max.
®
100
100
300
400
0.7
0.4
–
–
–
–
–
–
–
–
2.0 ReDdriver™
+ 0.3
PS8934D
PI2EQX5864C
2
C Control
Units
Unit
kHz
pF
μs
μs
μs
μs
μs
μs
μs
ns
ns
ns
V
V
V
V
07/08/09