DS25BR100TSD/NOPB National Semiconductor, DS25BR100TSD/NOPB Datasheet

IC BUFFER LVDS 3.125GBPS 8-LLP

DS25BR100TSD/NOPB

Manufacturer Part Number
DS25BR100TSD/NOPB
Description
IC BUFFER LVDS 3.125GBPS 8-LLP
Manufacturer
National Semiconductor
Type
Bufferr
Datasheet

Specifications of DS25BR100TSD/NOPB

Tx/rx Type
LVDS
Delay Time
350ps
Capacitance - Input
1.7pF
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
35mA
Mounting Type
Surface Mount
Package / Case
8-LLP
Supply Current
43mA
Supply Voltage Range
3V To 3.6V
Driver Case Style
LLP
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Msl
MSL 3 - 168 Hours
Filter Terminals
SMD
Logic Type
Buffer
Rohs Compliant
Yes
Data Rate
3.125Gbps
Data Rate Max
3.125Gbps
For Use With
DS25BR100EVK - BOARD EVALUATION DS25BR100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DS25BR100TSDTR

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© 2009 National Semiconductor Corporation
3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis and
Receive Equalization
General Description
The DS25BR100 and DS25BR101 are single channel 3.125
Gbps LVDS buffers optimized for high-speed signal trans-
mission over lossy FR-4 printed circuit board backplanes and
balanced metallic cables. Fully differential signal paths en-
sure exceptional signal integrity and noise immunity.
The DS25BR100 and DS25BR101 feature transmit pre-em-
phasis (PE) and receive equalization (EQ), making them ideal
for use as a repeater device. Other LVDS devices with similar
IO characteristics include the following products. The
DS25BR120 features four levels of pre-emphasis for use as
an optimized driver device, while the DS25BR110 features
four levels of equalization for use as an optimized receiver
device. The DS25BR150 is a buffer/repeater with the lowest
power consumption and does not feature transmit pre-em-
phasis nor receive equalization.
Wide input common mode range allows the receiver to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires minimal
space on the board while the flow-through pinout allows easy
board layout. On the DS25BR100 the differential input and
output is internally terminated with a 100Ω resistor to lower
return losses, reduce component count and further minimize
board space. For added design flexibility the 100Ω input ter-
minations on the DS25BR101 have been eliminated. This
enables a designer to adjust the termination for custom inter-
connect topologies and layout.
Typical Application
DS25BR100 / DS25BR101
201791
Features
Applications
DC - 3.125 Gbps low jitter, high noise immunity, low power
operation
Receive equalization reduces ISI jitter due to media loss
Transmit pre-emphasis drives lossy backplanes and
cables
On-chip 100Ω input and output termination minimizes
insertion and return losses, reduces component count and
minimizes board space. The DS25BR101 eliminates the
on-chip input termination for added design flexibility.
7 kV ESD on LVDS I/O pins protects adjoining
components
Small 3 mm x 3 mm LLP-8 space saving package
Clock and data buffering
Metallic cable driving and equalization
FR-4 equalization
20179110
August 11, 2009
www.national.com

Related parts for DS25BR100TSD/NOPB

DS25BR100TSD/NOPB Summary of contents

Page 1

... For added design flexibility the 100Ω input ter- minations on the DS25BR101 have been eliminated. This enables a designer to adjust the termination for custom inter- connect topologies and layout. Typical Application © 2009 National Semiconductor Corporation DS25BR100 / DS25BR101 Features ■ 3.125 Gbps low jitter, high noise immunity, low power operation ■ ...

Page 2

Device Information Device Function DS25BR100 Buffer / Repeater DS25BR101 Buffer / Repeater DS25BR110 Receiver DS25BR120 Driver DS25BR150 Buffer / Repeater Ordering Information NSID Package DS25BR100TSD 8 Lead LLP Package DS25BR100TSDX 8 Lead LLP Package DS25BR101TSD 8 Lead LLP Package DS25BR101TSDX ...

Page 3

Pin Descriptions Pin Name Pin Name EQ 1 IN OUT- 6 OUT+ 7 VCC 8 GND DAP Control Pins (PE and EQ) Truth Table ...

Page 4

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS Input Voltage (EQ, PE) LVDS Input Voltage (IN+, IN−) LVDS Differential Input Voltage (DS25BR100) LVDS Differential Input Voltage (DS25BR101) LVDS Output Voltage (OUT+, OUT− ...

Page 5

Symbol Parameter LVDS INPUT DC SPECIFICATIONS (IN+, IN-) V Input Differential Voltage (Note Differential Input High Threshold TH V Differential Input Low Threshold TL V Common Mode Voltage Range CMR I Input Current IN C Input Capacitance ...

Page 6

AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 11, 12) Symbol Parameter LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-) t Differential Propagation Delay High to Low PHLD t Differential Propagation Delay Low to High PLHD ...

Page 7

Symbol Parameter JITTER PERFORMANCE WITH PE = MEDIUM AND EQ = MEDIUM (Figures Random Jitter (RMS Value) RJ1D Input Test Channel E t RJ2D Output Test Channel B (Note 16) t Deterministic Jitter (Peak to Peak) DJ1D ...

Page 8

DC Test Circuits AC Test Circuits and Timing Diagrams Note: DS25BR101 requires external 100Ω input termination. www.national.com FIGURE 1. Differential Driver DC Test Circuit FIGURE 2. Differential Driver AC Test Circuit FIGURE 3. Propagation Delay Timing Diagram FIGURE 4. LVDS ...

Page 9

Pre-Emphasis and Equalization Test Circuits FIGURE 5. Pre-emphasis and Equalization Performance Test Circuit Note: DS25BR101 requires external 100Ω input termination. FIGURE 6. Equalization Performance Test Circuit Note: DS25BR101 requires external 100Ω input termination. 20179128 FIGURE 7. Test Channel Description 9 ...

Page 10

Test Channel Loss Characteristics The test channel was fabricated with Polyclad PCL-FR-370- Laminate/PCL-FRP-370 Prepreg materials (Dielectric con- Test Channel Length (inches Device Operation INPUT INTERFACING The DS25BR100/101 accepts ...

Page 11

Typical LVPECL Driver DC-Coupled Interface to DS25BR100 Input Note: DS25BR101 requires external 100Ω input termination. 20179113 11 www.national.com ...

Page 12

OUTPUT INTERFACING The DS25BR100/101 outputs signals compliant to the LVDS standard. It can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers and assumes that Typical Output DC-Coupled Interface to an ...

Page 13

Typical Performance Maximum Data Rate as a Function of CAT5e (Belden 1700A) Length A 2.5 Gbps NRZ PRBS-7 After 60" Differential FR-4 Stripline V:125 mV / DIV, H: DIV A 3.125 Gbps NRZ PRBS-7 After 60" Differential FR-4 ...

Page 14

Total Jitter as a Function of Data Rate Total Jitter as a Function of Input Amplitude Power Supply Current as a Function of Frequency www.national.com 20179137 Total Jitter as a Function of Data Rate 20179139 Total Jitter as a Function ...

Page 15

Physical Dimensions inches (millimeters) unless otherwise noted (See AN-1187 for PCB Design and Assembly Recommendations) Order Number DS25BR100TSD Order Number DS25BR101TSD NS Package Number SDA08A 15 www.national.com ...

Page 16

... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...

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