CYV15G0204RB-BGXC Cypress Semiconductor Corp, CYV15G0204RB-BGXC Datasheet - Page 14

• Manufacturer Part Number: CYV15G0204RB-BGXC
• Description: IC DESERIAL HOTLINK 256LBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYV15G0204RB-BGXC

• Function: Deserializer
• Data Rate: 1.485Gbps
• Input Type: PECL
• Output Type: LVTTL
• Number Of Inputs: 2
• Number Of Outputs: 2
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-02103 Rev. *C
Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
JTAG Support
The CYV15G0204RB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the TRGCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
Table 4. Device Control Latch Configuration Table
Table 5. Receive BIST Status Bits
1. Pulse RESET Low after device power-up. This operation
2. Set the static latch banks for the target channel. [Optional
3. Set the dynamic bank of latches for the target channel.
{BISTSTx, RXDx[0], RXDx[1]}
ADDR
(000b)
(001b)
(010b)
(101b)
(110b)
(111b)
resets both channels. Initialize the JTAG state machine to
its reset state as detailed in
step if the default settings match the desired configuration.]
Enable the Receive PLLs and set each channel for SMPTE
data reception (RXBISTx[1:0] = 01) or BIST data reception
(RXBISTx[1:0] = 10). [Required step]
0
1
2
5
6
7
Channel Type
A
A
A
B
B
B
000, 001
010
100
101
011
110
111
S
S
D
S
S
D
SDASEL2A[1]
SDASEL2B[1]
RXBISTB[1]
RXBISTA[1]
DATA6
1
1
JTAG
BIST Data Compare. Character compared correctly.
BIST Last Good. Last Character of BIST sequence detected and valid.
Reserved.
BIST Last Bad. Last Character of BIST sequence detected invalid.
BIST Start. Receive BIST is enabled on this channel, but character compares have not yet
commenced. This also indicates a PLL Out of Lock condition.
BIST Error. While comparing characters, a mismatch was found in one or more of the character
bits.
BIST Wait. The receiver is comparing characters. but has not yet found the start of BIST
character to enable the LFSR.
Support.
SDASEL2A[0]
SDASEL2B[0]
RXPLLPDA
RXPLLPDB
DATA5
0
0
SDASEL1A[1]
SDASEL1B[1]
RXBISTA[0]
RXBISTB[0]
DATA4
X
X
To ensure valid device operation after power-up (including
non-JTAG operation), the JTAG state machine should also be
initialized to a reset state. This should be done in addition to
the device reset (using RESET). The JTAG state machine can
be initialized using TRST (asserting it LOW and de-asserting
it or leaving it asserted), or by asserting TMS HIGH for at least
5 consecutive TCLK cycles. This is necessary in order to
ensure that the JTAG controller does not enter any of the test
modes after device power-up. In this JTAG reset state, the rest
of the device will be in normal operation.
Note. The order of device reset (using RESET) and JTAG
initialization does not matter.
3-Level Select Inputs
Each 3-Level select inputs reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0204RB is ‘0C811069’x.
(Receive BIST = Enabled)
SDASEL1A[0]
SDASEL1B[0]
Receive BIST Status
DATA3
X
X
X
X
Description
ROE2A
ROE2B
DATA2
X
X
0
0
ROE1A
ROE1B
DATA1
X
X
0
0
CYV15G0204RB
TRGRATEA
TRGRATEB
RXRATEA
RXRATEB
DATA0
X
X
Page 14 of 24
101011
101100
101011
101100
101111
101111
Reset
Value
[+] Feedback