MAX9217ETM+T Maxim Integrated Products, MAX9217ETM+T Datasheet - Page 9

• Manufacturer Part Number: MAX9217ETM+T
• Description: IC SERIALIZER LVDS 48-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX9217ETM+T

• Function: Serializer
• Data Rate: 700Mbps
• Input Type: LVTTL/LVCMOS
• Output Type: LVDS
• Number Of Inputs: 27
• Number Of Outputs: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8. Peak-to-Peak Output Offset Voltage
The MAX9217 DC-balanced serializer operates at a
parallel clock frequency of 3MHz to 35MHz, serializing
18 bits of parallel video data RGB_IN[17:0] when the
data enable input DE_IN is high, or 9 bits of parallel
control data CNTL_IN[8:0] when DE_IN is low. The
RGB video input data are encoded using 2 overhead
bits, EN0 and EN1, resulting in a serial word length of
20 bits (Table 1). Control inputs are mapped to 19 bits
and encoded with 1 overhead bit, EN0, also resulting in
a 20-bit serial word. Encoding reduces EMI and main-
Table 1. Serial Video Phase Word Format
Bit 0 is the LSB and is serialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Table 2. Serial Control Phase Word Format
Bit 0 is the LSB and is serialized first. C[8:0] are the control inputs.
EN0
E N 0
0
0
((OUT+) + (OUT-)) / 2
EN1
C0
1
1
OUT+
OUT-
C0
S0
2
2
_______________________________________________________________________________________
C0
S1
3
3
Detailed Description
C1
S2
4
4
C1
S3
5
5
C1
S4
6
6
V
OS(P-P)
C2
S5
7
7
DC-Balanced LVDS Serializer
C2
S6
8
8
C2
S7
9
9
C3
10
10
S8
tains DC balance across the serial cable. Two transition
words, which contain a unique bit sequence, are insert-
ed at the transition boundaries of video-to-control and
control-to-video phases.
Control data inputs C0 to C4 are mapped to 3 bits each
in the serial control word (Table 2). At the deserializer,
2 or 3 bits at the same state determine the state of the
recovered bit, providing single bit-error tolerance for
C0 to C4. Control data that may be visible if an error
occurs, such as VSYNC and HSYNC, can be connect-
ed to these inputs. Control data inputs C5 to C8 are
mapped to 1 bit each.
27-Bit, 3MHz-to-35MHz
C3
11
S9
11
S10
C3
12
12
S11
V
C4
13
13
OS(P-P)
S12
C4
14
14
S13
C4
15
15
S14
C5
16
16
S15
C6
17
17
S16
C7
18
18
S17
C8
19
19
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