LM2502SQX/NOPB National Semiconductor, LM2502SQX/NOPB Datasheet - Page 25

• Manufacturer Part Number: LM2502SQX/NOPB
• Description: IC SER/DESER MPL DISPL 40-LLP
• Manufacturer: National Semiconductor
• Series: LMr

Specifications of LM2502SQX/NOPB

• Function: Serializer/Deserializer
• Data Rate: 307Mbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 22
• Number Of Outputs: 3
• Voltage - Supply: 1.7 V ~ 3.3 V
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM2502SQX

Application Information
for the LM2502 chipset is 245 Mbps (307 Mbps raw - in-
cludes overhead), thus there is adequate bandwidth for this
application and even larger resolution displays.
Figure 21 shows the typical timing of the RGB application.
The 6X PLL setting (PLLCON[2:0] = 010’b) is selected. The
PCLK is applied to both the WR* and CLK inputs on the
Master. The rising edge on the WR* (PCLK) signal samples
the data by the Master for serialization. The CLK input can
be the PCLK (if timing requirements are met) or a synchro-
nous clock to the PCLK signal. The HS connects to the CS1*
(Continued)
FIGURE 21. RGB565 Application Timing
25
signal and the HS* (inverted HS) is connected to the CS2*.
With this configuration there will always be a valid CS* LOW
on the Master input. The RGB information is then serialized
and passed to the Slave via the MPL bus. It takes 5 MC
cycles to complete the transfer and with the 6X PLL setting,
there will be two idle bits on the MD (1 MC cycle) lines before
the next transfer. Recovery of the RGB interface (RGB565,
HS, VS and PCLK) is provided at the Slave output. The
PCLK is slightly shifted later in time (1 MC cycle) but ad-
equate timing margin (increased set, shorted hold) is still
provided.
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