MAX9244EUM+D Maxim Integrated Products, MAX9244EUM+D Datasheet - Page 21

• Manufacturer Part Number: MAX9244EUM+D
• Description: IC DESERIALIZER 21BIT 48-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX9244EUM+D

• Function: Deserializer
• Data Rate: 306Mbps
• Input Type: LVDS
• Output Type: LVTTL, LVCMOS
• Number Of Inputs: 3
• Number Of Outputs: 21
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SSG and DCB provides the proper mid-level voltage
under conditions of low input current. The mid-level
input current must not be greater than ±10µA, and the
mid-level logic state cannot be driven with an external
voltage source.
The MAX9242/MAX9244/MAX9246/MAX9254 ESD toler-
ance is rated for Human Body Model, IEC 61000-4-2
and ISO 10605. The ISO 10605 and IEC 61000-4-2
standards specify ESD tolerance for electronic sys-
tems. All LVDS inputs on the MAX9242/MAX9244/
MAX9246/MAX9254 meet ISO 10605 ESD protection at
±30kV Air-Gap Discharge and ±6kV Contact Discharge
and IEC 61000-4-2 ESD protection at ±15kV Air-Gap
Discharge and ±8kV Contact Discharge. All other pins
meet the Human Body Model ESD tolerance of ±2.5kV.
The Human Body Model discharge components are C
= 100pF and R
2 discharge components are C
330Ω (see Figure 22). The ISO 10605 discharge com-
ponents are C
Figure 21. Human Body ESD Test Circuit
Figure 22. IEC 61000-4-2 Contact Discharge ESD Test Circuit
VOLTAGE
SOURCE
VOLTAGE
SOURCE
HIGH-
HIGH-
IEC 61000-4-2 Level 4 and ISO 10605
DC
DC
CHARGE-CURRENT-
CHARGE-CURRENT-
S
LIMIT RESISTOR
LIMIT RESISTOR
D
= 330pF and R
= 1.5kΩ (Figure 21). The IEC 61000-4-
______________________________________________________________________________________
150pF
21-Bit Deserializers with Programmable
100pF
C
C
S
S
RESISTANCE
RESISTANCE
DISCHARGE
DISCHARGE
STORAGE
CAPACITOR
STORAGE
CAPACITOR
330Ω
1.5kΩ
R2
R
D
D
= 2kΩ (Figure 23).
S
Spread Spectrum and DC Balance
= 150pF and R
ESD Protection
DEVICE
UNDER
DEVICE
UNDER
TEST
TEST
D
=
S
Figure 23. ISO 10605 Contact Discharge ESD Test Circuit
PROCESS: CMOS
TOP VIEW
VOLTAGE
SOURCE
HIGH-
DC
RxCLKOUT
LVDSGND
LVDSGND
RxCLKIN+
PWRDWN
RxCLKIN-
LVDSV
RxOUT17
RxOUT18
RxOUT19
RxOUT20
CHARGE-CURRENT-
PLLGND
PLLGND
RxOUT0
PLLV
RxIN1+
RxIN2+
RxIN1-
RxIN2-
LIMIT RESISTOR
RxIN0+
RxIN0-
GND
DCB
SSG
CC
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
330pF
C
S
MAX9242
MAX9244
MAX9246
MAX9254
TSSOP
RESISTANCE
DISCHARGE
Pin Configuration
STORAGE
CAPACITOR
Chip Information
2kΩ
R
D
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
RxOUT16
RxOUT15
RxOUT14
GND
RxOUT13
V
RxOUT12
RxOUT11
RxOUT10
GND
RxOUT9
V
RxOUT8
RxOUT7
RxOUT6
GND
RxOUT5
RxOUT4
RxOUT3
V
GND
RxOUT2
RxOUT1
CCO
CC
CCO
CCO
DEVICE
UNDER
TEST
21