MAX9244EUM+D Maxim Integrated Products, MAX9244EUM+D Datasheet - Page 19

• Manufacturer Part Number: MAX9244EUM+D
• Description: IC DESERIALIZER 21BIT 48-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX9244EUM+D

• Function: Deserializer
• Data Rate: 306Mbps
• Input Type: LVDS
• Output Type: LVTTL, LVCMOS
• Number Of Inputs: 3
• Number Of Outputs: 21
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 20. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
The recommended link power-up sequence is to power
up the serializer, wait until the serializer PLL locks, and
then power up the deserializer. This sequence prevents
the deserializer from seeing an undriven or unstable
input when powering up.
Driving PWRDWN low puts the outputs in high imped-
ance, stops the PLL, and reduces supply current to
50µA or less. Driving PWRDWN high drives the outputs
low until the PLL locks. The outputs of two deserializers
can be bused to form a 2:1 mux with the outputs con-
trolled by PWRDWN. Wait 100ns between disabling one
deserializer (driving PWRDWN low) and enabling the
second one (driving PWRDWN high) to avoid con-
tention of the bused outputs.
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
V
CC
PWRDWN
, V
TxCLK IN
CCO
TxIN
, PLLV
7
7
7
CC
______________________________________________________________________________________
21-Bit Deserializers with Programmable
(7 + 2):1
(7 + 2):1
(7 + 2):1
, and LVDSV
PLL
Link Power-Up Sequence
MAX9209/MAX9213
Power-Supply Bypassing
21:3 SERIALIZER
CC
Spread Spectrum and DC Balance
with high-frequency,
R
O
PWRDWN
TxOUT
TxCLK OUT
SURFACE-MOUNT CAPACITORS
HIGH-FREQUENCY CERAMIC
surface-mount ceramic 0.1µF and 0.001µF capacitors in
parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin.
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
nals separated to prevent crosstalk. A four-layer PC
board with separate layers for power, ground, LVDS
inputs, and digital signals is recommended. Layout PC
board traces for 100Ω differential characteristic imped-
ance. The trace dimensions depend on the type of
100Ω
100Ω
100Ω
100Ω
RxCLK IN
R
RxIN__
T
MAX9242/MAX9244/MAX9246/MAX9254
3:21 DESERIALIZER
Cables and Connectors
1:(9 - 2)
1:(9 - 2)
1:(9 - 2)
+ FIFO
+ FIFO
+ FIFO
PLL1 +
SSPLL
Board Layout
7
7
7
RxOUT_
PWRDWN
RxCLK OUT
19