AD9891KBC Analog Devices Inc, AD9891KBC Datasheet - Page 15

• Manufacturer Part Number: AD9891KBC
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9891KBC

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

HORIZONTAL CLAMPING AND BLANKING
The AD9891/AD9895’s horizontal clamping and blanking pulses
are fully programmable to suit a variety of applications. As with
the vertical timing generation, individual sequences are defined
for each signal, which are then organized into multiple regions
during image readout. This allows the dark pixel clamping and
blanking patterns to be changed at each stage of the readout in
order to accommodate different image transfer timing and high
speed line shifts.
Individual CLPOB, CLPDM, and PBLK Sequences
The AFE horizontal timing consists of CLPOB, CLPDM, and
PBLK, as shown in Figure 13. These three signals are indepen-
dently programmed using the registers in Table III. SPOL is
the start polarity for the signal, and TOG1 and TOG2 are the
first and second toggle positions of the pulse. All three signals
are active low and should be programmed accordingly. Up to
four individual sequences can be created for each signal.
REV. A
H1/H3
HBLK
HBLK
THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1)
PROGRAMMABLE SETTINGS:
1: 1ST TOGGLE POSITION = START OF BLANKING
2: 2ND TOGGLE POSITION = END OF BLANKING
HD
HD
CLPOB
CLPDM
PROGRAMMABLE SETTINGS:
1: START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
2: 1ST TOGGLE POSITION
3: 2ND TOGGLE POSITION
PBLK
H1/H3
H2/H4
HD
1
1
BLANK
2
Figure 14. Horizontal Blanking (HBLK) Pulse Placement
CLAMP
2
Figure 13. Clamp and Preblank Pulse Placement
3
Figure 15. HBLK Masking Control
–15–
To simplify the programming requirements, the CLPDM signal
will track the CLPOB signal by default. If separate control of
the CLPDM signal is desired, the SINGLE_CLAMP Register
(Addr x031) should be set LOW.
Individual HBLK Sequences
The HBLK programmable timing shown in Figure 14 is similar
to CLPOB, CLPDM, and PBLK. However, there is no start
polarity control. Only the toggle positions are used to designate
the start and the stop positions of the blanking period. Addition-
ally, there is a polarity control, HBLKMASK, that designates the
polarity of the horizontal clock signals H1–H4 during the blank-
ing period. Setting HBLKMASK high will set H1 = H3 = Low
and H2 = H4 = High during the blanking, as shown in Figure 15.
Up to four individual sequences are available for HBLK.
Horizontal Sequence Control
The AD9891/AD9895 use sequence change positions (SCP)
and sequence pointers (SPTR) to organize the individual hori-
BLANK
CLAMP
AD9891/AD9895