54ABT573W-QML National Semiconductor, 54ABT573W-QML Datasheet

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54ABT573W-QML

Manufacturer Part Number
54ABT573W-QML
Description
Manufacturer
National Semiconductor
Type
D-Typer
Datasheet

Specifications of 54ABT573W-QML

Logic Family
ABT
Number Of Bits
8
Number Of Elements
1
Latch Mode
Transparent
Polarity
Non-Inverting
Technology
BiCMOS
Output Type
3-State
Package Type
CPAK
Propagation Delay Time
7.7ns
Operating Supply Voltage (typ)
5V
High Level Output Current
-24mA
Low Level Output Current
48mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-55C to 125C
Operating Temperature Classification
Military
Mounting
Surface Mount
Pin Count
20
Lead Free Status / Rohs Status
Not Compliant
© 1998 National Semiconductor Corporation
54ABT573
Octal D-Type Latch with TRI-STATE
General Description
The ’ABT573 is an octal latch with buffered common Latch
Enable (LE) and buffered common Output Enable (OE) in-
puts.
This device is functionally identical to the ’ABT373 but has
different pinouts.
Features
n Inputs and outputs on opposite sides of package allow
n Useful as input or output port for microprocessors
Ordering Code
Connection Diagram
TRI-STATE
54ABT573J-QML
54ABT573W-QML
54ABT573E-QML
easy interface with microprocessors
®
is a registered trademark of National Semiconductor Corporation.
Military
for DIP and Cerpack
Pin Assignment
DS100219
DS100219-1
J20A
W20A
E20A
Package
Number
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
n Functionally identical to ’ABT373
n TRI-STATE outputs for bus interfacing
n Output sink capability of 48 mA, source capability of
n Output switching specified for both 50 pF and 250 pF
n Guaranteed latchup protection
n High impedance glitch-free bus loading during entire
n Nondestructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9321901
D
LE
OE
O
24 mA
loads
power up and power down
0
0
Names
–D
–O
Pin
7
7
®
Data Inputs
Latch Enable Input (Active HIGH)
TRI-STATE Output Enable Input
(Active LOW)
TRI-STATE Latch Outputs
Outputs
Package Description
Pin Assignment
for LCC
Description
DS100219-39
www.national.com
July 1998

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54ABT573W-QML Summary of contents

Page 1

... Features n Inputs and outputs on opposite sides of package allow easy interface with microprocessors n Useful as input or output port for microprocessors Ordering Code Military 54ABT573J-QML 54ABT573W-QML 54ABT573E-QML Connection Diagram Pin Assignment for DIP and Cerpack DS100219-1 TRI-STATE ® registered trademark of National Semiconductor Corporation. ...

Page 2

Functional Description The ’ABT573 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the D inputs enters the latches. In this condition the n latches are transparent, i.e., a latch output ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic V Pin Potential to CC Ground Pin Input Voltage (Note 2) Input Current (Note 2) − +5.0 mA Voltage Applied to Any Output in ...

Page 4

DC Electrical Characteristics Symbol Parameter V Quiet Output Maximum Dynamic V OLP V Quiet Output Minimum Dynamic V OLV Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output ...

Page 5

Capacitance (Continued pF Temperature ( PLH Output Switching, Data to Output = 50 pF Temperature ( PZH Output Switching Output Dashed lines ...

Page 6

Capacitance (Continued Temperature ( PHZ A 1 Output Switching Output T LOW vs Temperature ( SET A 1 Output Switching, Data HIGH vs Temperature (T HOLD A 1 Output ...

Page 7

Capacitance (Continued pF Temperature ( PLH Outputs Switching, Data to Output = 50 pF Temperature ( PZH Outputs Switching Output = 50 ...

Page 8

Capacitance (Continued Load Capacitance T PLH 1 Output Switching, Data to Output T vs Load Capacitance T PLH 8 Outputs Switching, Data to Output T vs Load Capacitance T PZH 8 Outputs Switching Output Dashed lines ...

Page 9

Capacitance (Continued pF Temperature ( PLH Output Switching Output = 50 pF Temperature ( PLH Outputs Switching Output T and ...

Page 10

AC Loading *Includes jig and probe capacitance FIGURE 1. Test Load FIGURE 2. Test Input Signal Levels Amplitude Rep. Rate t w 3.0V 1 MHz 500 ns FIGURE 3. Test Input Signal Requirements FIGURE 4. Propagation Delay Waveforms for Inverting ...

Page 11

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Ceramic Leadless Chip Carrier NS Package Number E20A 20-Lead Ceramic Dual-In-Line NS Package Number J20A 11 www.national.com ...

Page 12

... National Semiconductor Asia Pacific Customer Fax: +49 (0) 1 80-530 85 86 Response Group Email: europe.support@nsc.com Tel: 65-2544466 Fax: 65-2504466 Tel: +49 (0) 1 80-532 78 32 Email: sea.support@nsc.com Tel: +49 (0) 1 80-534 16 80 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 ...

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