AD9805JS Analog Devices Inc, AD9805JS Datasheet - Page 17

• Manufacturer Part Number: AD9805JS
• Description: IC CCD SIGNAL PROC 10BIT 64-PQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9805JS

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: Microprocessor
• Current - Supply: 86mA
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

Calculating Overall Gain
The overall gain for the AD9807/AD9805 can accommodate a
wide range of input voltage spans. The total gain is a composite
of analog gain (from the PGAs), digital gain (from the digital
multiplier) and the input span setting for the A/D (2 V or 4 V). To
determine the overall gain setting for the AD9807/AD9805, always
multiply the PGA gain setting by the digital gain setting. In
addition, the 2 V/4 V reference option can effectively provide
analog gain for input signals less than 2 V p-p.
For example, with the PGA gain equal to 1 (gain setting equals
all “zeros”) and the digital multiplier equal to 1, the minimum
gain equals 1. With these settings, input signals can be as large
as 2 V or 4 V depending on the reference setting. Alternatively,
with the PGA gain equal to 4 (gain setting equals all “ones”)
and the digital multiplier equal to 8, the maximum gain equals
32. With the A/D reference span set to 2 V, an input signal span
as small as 62.5 mV p-p will produce a digital output spanning
from all “zeros” to all “ones.” For ranges between 62.5 mV and
4 V, see the Digital Gain and Analog Gain sections of the data
sheet.
Analog Gain
The transfer function of the PGA is:
where x is the decimal representation of the settings in the PGA
gain register. Figure 16 shows the graph of this transfer
function on both a linear and logarithmic scale. The transfer
function is approximately linear in dB.
Digital Gain
The digital multiplier section of the AD9807/AD9805 allows the
user to apply gain in addition to that afforded by the analog
PGA. The minimum gain of the digital multiplier is always 1.
The user sets the maximum gain of the digital multiplier to be 8,
4, or 2 with Bits 0–2 in the Configuration Register. (The max
gain is the same for all three channels.) The digital gain
applied to the output from the digital subtracter is calculated
using the equation:
REV. 0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0
Overall Gain = Analog Gain Digital Gain
1
Figure 16. PGA Transfer Function
Digital Gain
2
Analog Input
3
4
5
PGA GAIN SETTING
6
1
GAIN (dB)
7
1 3
Gain n:0
8
9
Y
4
10 11 12
15 x
GAIN
15
X
13
14 15
12
10
8
6
4
2
0
–17–
where GAIN<n:0> is the decimal representation of the GAIN
bus data bits, Y = 4096 for the AD9807, Y = 1024 for the
AD9805, and X equals 1, 3 or 7 depending on Bits 0–2 in the
Configuration Register.
Overall Transfer Function
The overall transfer function for the AD9807 can be calculated
as follows:
Choosing the Input Coupling Capacitors
Because of the dc offset present at the output of CCDs, it is likely
that these outputs will require some form of dc restoration to be
compatible with the input requirements of the AD9807/AD9805.
To simplify input level shifting, a dc blocking capacitor may be
used in conjunction with the internal biasing circuits of the
AD9807/AD9805 to accomplish the necessary dc restoration.
Figure 17 shows the equivalent analog input for the VINR,
VING and VINB inputs.
Enabling CDS functionality and Line Clamp Mode with Bits 0,
6 and 7 in Configuration Register 2 allows switch S1 to turn on
when STRTLN is low and CDSCLK1 goes high. This connects
a 5 k biasing resistor to the inputs. This arrangement acts to
bias the average level of the input signal at voltage, V
voltage, V
ting. Specifically, for gain settings from 0 to 5, V
for gain settings from 10 to 15, V
tings between 5 and 10, V
The size of the coupling capacitor is dependent on several
factors including signal swing, allowable droop, and acquisition
time. The following procedure shows how to determine the
recommended range of capacitors.
Calculating C
The maximum capacitor value is largely dependent on the
degree of accuracy and how quickly the input signal must be
level-shifted into the valid input range of the degree of accuracy.
Other factors affecting the speed of the capacitor charging or
V
CDSCLK2
CDSCLK1
D
IN
Figure 17. Equivalent Analog Inputs (VINR, VING, and
VINB)
STRTLN
OUT
C
ADC
= [ADC
BIAS
OUT
, changes depending on the selected PGA gain set-
AD9807/AD9805
MAX
OUT
V
+ Offset Register – Offset Bus][Digital Gain]
IN
BIAS
InputOffset
CONFIG
REG 2<7>
CONFIG
REG 2<0>
CONFIG
REG 2<6>
decreases linearly from 4 V to 3 V.
2 V
BIAS
AD9807/AD9805
REF
I
5k
V
BIAS
S1
BIAS
equals 3 V. For gain set-
PGA Gain
4pF
4pF
BIAS
CDS
equals 4 V;
4096
BIAS
. The